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GET /api/patches/2216886/?format=api
{ "id": 2216886, "url": "http://patchwork.ozlabs.org/api/patches/2216886/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-49-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-49-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:43", "name": "[v2,48/65] target/arm: GICv5 cpuif: Implement GICR CDIA command", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d1c51280a17767163afdde09c157b61d6ef697fa", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-49-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216886/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216886/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=JCH9gFCF;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyqJ4MV3z1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:20:12 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CZ-0007cC-Qv; Fri, 27 Mar 2026 07:18:07 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CJ-00076y-Mk\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400", "from mail-wr1-x433.google.com ([2a00:1450:4864:20::433])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CH-0008OQ-Az\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400", "by mail-wr1-x433.google.com with SMTP id\n ffacd0b85a97d-43b40003d13so1406564f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:48 -0700 (PDT)", "from lanath.. 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It returns a\nvalue corresponding to the HPPI for the current physical interrupt\ndomain, if any, and moves that interrupt to being Active.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/tcg/gicv5-cpuif.c | 101 +++++++++++++++++++++++++++++++++++\n target/arm/tcg/trace-events | 2 +\n 2 files changed, 103 insertions(+)", "diff": "diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 36bbb70c4a..09870e0b09 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -39,6 +39,10 @@ FIELD(GIC_CDHM, HM, 32, 1)\n FIELD(GIC_CDRCFG, ID, 0, 24)\n FIELD(GIC_CDRCFG, TYPE, 29, 3)\n \n+FIELD(GICR_CDIA, ID, 0, 24)\n+FIELD(GICR_CDIA, TYPE, 29, 3)\n+FIELD(GICR_CDIA, VALID, 32, 1)\n+\n FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4)\n FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4)\n FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4)\n@@ -463,6 +467,93 @@ static uint64_t gic_icc_hppir_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)\n return hppi.intid;\n }\n \n+static bool gic_hppi_is_nmi(CPUARMState *env, GICv5PendingIrq hppi,\n+ GICv5Domain domain)\n+{\n+ /*\n+ * For GICv5 an interrupt is an NMI if it is signaled with\n+ * Superpriority and SCTLR_ELx.NMI for the current EL is 1. GICR\n+ * CDIA/CDNMIA always work on the current interrupt domain, so we\n+ * do not need to consider preemptive interrupts. This means that\n+ * the interrupt has Superpriority if and only if it has priority 0.\n+ */\n+ return hppi.prio == 0 && arm_sctlr(env, arm_current_el(env)) & SCTLR_NMI;\n+}\n+\n+static uint64_t gicr_cdia_read(CPUARMState *env, const ARMCPRegInfo *ri)\n+{\n+ /* Acknowledge HPPI in the current interrupt domain */\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+ GICv5PendingIrq hppi = gic_hppi(env, domain);\n+ GICv5IntType type = FIELD_EX64(hppi.intid, INTID, TYPE);\n+ uint32_t id = FIELD_EX64(hppi.intid, INTID, ID);\n+\n+ bool cdnmia = ri->opc2 == 1;\n+\n+ if (!hppi.intid) {\n+ /* No interrupt available to acknowledge */\n+ trace_gicv5_gicr_cdia_fail(domain,\n+ \"no available interrupt to acknowledge\");\n+ return 0;\n+ }\n+ assert(hppi.prio != PRIO_IDLE);\n+\n+ if (gic_hppi_is_nmi(env, hppi, domain) != cdnmia) {\n+ /* GICR CDIA only acknowledges non-NMI; GICR CDNMIA only NMI */\n+ trace_gicv5_gicr_cdia_fail(domain,\n+ cdnmia ? \"CDNMIA but HPPI is not NMI\" :\n+ \"CDIA but HPPI is NMI\");\n+ return 0;\n+ }\n+\n+ trace_gicv5_gicr_cdia(domain, hppi.intid);\n+\n+ /*\n+ * The interrupt becomes Active. If the handling mode of the\n+ * interrupt is Edge then we also clear the pending state.\n+ */\n+\n+ /*\n+ * Set the appropriate bit in the APR to track active priorities.\n+ * We do this now so that when gic_recalc_ppi_hppi() or\n+ * gicv5_activate() cause a re-evaluation of HPPIs they use the\n+ * right (new) running priority.\n+ */\n+ env->gicv5_cpuif.icc_apr[domain] |= (1 << hppi.prio);\n+ switch (type) {\n+ case GICV5_PPI:\n+ {\n+ uint32_t ppireg, ppibit;\n+\n+ assert(id < GICV5_NUM_PPIS);\n+ ppireg = id / 64;\n+ ppibit = 1 << (id % 64);\n+\n+ env->gicv5_cpuif.ppi_active[ppireg] |= ppibit;\n+ if (!(env->gicv5_cpuif.ppi_hm[ppireg] & ppibit)) {\n+ /* handling mode is Edge: clear pending */\n+ env->gicv5_cpuif.ppi_pend[ppireg] &= ~ppibit;\n+ }\n+ gic_recalc_ppi_hppi(env);\n+ break;\n+ }\n+ case GICV5_LPI:\n+ case GICV5_SPI:\n+ /*\n+ * Send an Activate command to the IRS, which, despite the\n+ * name of the stream command, does both \"set Active\" and\n+ * \"maybe set not Pending\" as a single atomic action.\n+ */\n+ gicv5_activate(gic, id, domain, type, false);\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ return hppi.intid | R_GICR_CDIA_VALID_MASK;\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -520,6 +611,16 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n .writefn = gic_cdhm_write,\n },\n+ { .name = \"GICR_CDIA\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 3, .opc2 = 0,\n+ .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .readfn = gicr_cdia_read,\n+ },\n+ { .name = \"GICR_CDNMIA\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 3, .opc2 = 1,\n+ .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .readfn = gicr_cdia_read,\n+ },\n { .name = \"ICC_IDR0_EL1\", .state = ARM_CP_STATE_AA64,\n .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 2,\n .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,\ndiff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events\nindex 7dc5f781c5..13e15cfcfc 100644\n--- a/target/arm/tcg/trace-events\n+++ b/target/arm/tcg/trace-events\n@@ -3,3 +3,5 @@\n \n # gicv5-cpuif.c\n gicv5_recalc_ppi_hppi(int domain, uint32_t id, uint8_t prio) \"domain %d new PPI HPPI id 0x%x prio %u\"\n+gicv5_gicr_cdia_fail(int domain, const char *reason) \"domain %d CDIA attempt failed: %s\"\n+gicv5_gicr_cdia(int domain, uint32_t id) \"domain %d CDIA acknowledge of interrupt 0x%x\"\n", "prefixes": [ "v2", "48/65" ] }