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GET /api/patches/2216928/?format=api
{ "id": 2216928, "url": "http://patchwork.ozlabs.org/api/patches/2216928/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-59-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-59-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:53", "name": "[v2,58/65] hw/arm/virt: Pull \"wire CPU interrupts\" out of create_gic()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5623bb21818397a2760930b8d0cbc08f6a024a85", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-59-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216928/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216928/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=U3nCnWRK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyxr6YNkz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:25:52 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Dp-0001hC-1W; Fri, 27 Mar 2026 07:19:25 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CV-0007Tr-Jf\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:05 -0400", "from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CT-00008s-9g\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:02 -0400", "by mail-wr1-x42b.google.com with SMTP id\n ffacd0b85a97d-43b5bded412so1432804f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:58 -0700 (PDT)", "from lanath.. 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As a preliminary to\nsplitting it up, pull out the \"wire the CPU interrupts to the GIC PPI\ninputs\" code out into its own function. This is a long and\nself-contained piece of code that is the main thing that we need to\ndo basically the same way for GICv2 and GICv3.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/arm/virt.c | 126 +++++++++++++++++++++++++++-----------------------\n 1 file changed, 68 insertions(+), 58 deletions(-)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 544605244b..5a2cb81919 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -794,13 +794,79 @@ static bool gicv3_nmi_present(VirtMachineState *vms)\n (vms->gic_version != VIRT_GIC_VERSION_2);\n }\n \n+static void gic_connect_ppis(VirtMachineState *vms)\n+{\n+ /*\n+ * Wire the outputs from each CPU's generic timer and the GICv3\n+ * maintenance interrupt signal to the appropriate GIC PPI inputs,\n+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the\n+ * CPU's inputs.\n+ */\n+ MachineState *ms = MACHINE(vms);\n+ unsigned int smp_cpus = ms->smp.cpus;\n+ SysBusDevice *gicbusdev = SYS_BUS_DEVICE(vms->gic);\n+\n+ for (int i = 0; i < smp_cpus; i++) {\n+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i));\n+ int intidbase = NUM_IRQS + i * GIC_INTERNAL;\n+ /*\n+ * Mapping from the output timer irq lines from the CPU to the\n+ * GIC PPI inputs we use for the virt board.\n+ */\n+ const int timer_irq[] = {\n+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,\n+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,\n+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,\n+ [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,\n+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,\n+ [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,\n+ [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,\n+ };\n+\n+ for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {\n+ qdev_connect_gpio_out(cpudev, irq,\n+ qdev_get_gpio_in(vms->gic,\n+ intidbase + timer_irq[irq]));\n+ }\n+\n+ if (vms->gic_version != VIRT_GIC_VERSION_2) {\n+ qemu_irq irq = qdev_get_gpio_in(vms->gic,\n+ intidbase + ARCH_GIC_MAINT_IRQ);\n+ qdev_connect_gpio_out_named(cpudev, \"gicv3-maintenance-interrupt\",\n+ 0, irq);\n+ } else if (vms->virt) {\n+ qemu_irq irq = qdev_get_gpio_in(vms->gic,\n+ intidbase + ARCH_GIC_MAINT_IRQ);\n+ sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);\n+ }\n+\n+ qdev_connect_gpio_out_named(cpudev, \"pmu-interrupt\", 0,\n+ qdev_get_gpio_in(vms->gic, intidbase\n+ + VIRTUAL_PMU_IRQ));\n+\n+ sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));\n+ sysbus_connect_irq(gicbusdev, i + smp_cpus,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));\n+ sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));\n+ sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));\n+\n+ if (vms->gic_version != VIRT_GIC_VERSION_2) {\n+ sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_NMI));\n+ sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));\n+ }\n+ }\n+}\n+\n static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n {\n MachineState *ms = MACHINE(vms);\n /* We create a standalone GIC */\n SysBusDevice *gicbusdev;\n const char *gictype;\n- int i;\n unsigned int smp_cpus = ms->smp.cpus;\n uint32_t nb_redist_regions = 0;\n int revision;\n@@ -899,63 +965,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n }\n }\n \n- /* Wire the outputs from each CPU's generic timer and the GICv3\n- * maintenance interrupt signal to the appropriate GIC PPI inputs,\n- * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the\n- * CPU's inputs.\n- */\n- for (i = 0; i < smp_cpus; i++) {\n- DeviceState *cpudev = DEVICE(qemu_get_cpu(i));\n- int intidbase = NUM_IRQS + i * GIC_INTERNAL;\n- /* Mapping from the output timer irq lines from the CPU to the\n- * GIC PPI inputs we use for the virt board.\n- */\n- const int timer_irq[] = {\n- [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,\n- [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,\n- [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,\n- [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,\n- [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,\n- [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,\n- [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,\n- };\n-\n- for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {\n- qdev_connect_gpio_out(cpudev, irq,\n- qdev_get_gpio_in(vms->gic,\n- intidbase + timer_irq[irq]));\n- }\n-\n- if (vms->gic_version != VIRT_GIC_VERSION_2) {\n- qemu_irq irq = qdev_get_gpio_in(vms->gic,\n- intidbase + ARCH_GIC_MAINT_IRQ);\n- qdev_connect_gpio_out_named(cpudev, \"gicv3-maintenance-interrupt\",\n- 0, irq);\n- } else if (vms->virt) {\n- qemu_irq irq = qdev_get_gpio_in(vms->gic,\n- intidbase + ARCH_GIC_MAINT_IRQ);\n- sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);\n- }\n-\n- qdev_connect_gpio_out_named(cpudev, \"pmu-interrupt\", 0,\n- qdev_get_gpio_in(vms->gic, intidbase\n- + VIRTUAL_PMU_IRQ));\n-\n- sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));\n- sysbus_connect_irq(gicbusdev, i + smp_cpus,\n- qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));\n- sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,\n- qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));\n- sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,\n- qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));\n-\n- if (vms->gic_version != VIRT_GIC_VERSION_2) {\n- sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,\n- qdev_get_gpio_in(cpudev, ARM_CPU_NMI));\n- sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,\n- qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));\n- }\n- }\n+ gic_connect_ppis(vms);\n \n fdt_add_gic_node(vms);\n }\n", "prefixes": [ "v2", "58/65" ] }