diff mbox series

[39/44] RISC-V/testsuite: Add branchless cases for generic FP cond adds

Message ID alpine.DEB.2.20.2311190132400.5892@tpp.orcam.me.uk
State New
Headers show
Series RISC-V: Various if-conversion fixes and improvements | expand

Commit Message

Maciej W. Rozycki Nov. 19, 2023, 5:43 a.m. UTC 
Verify, for generic floating-point conditional-add operations that have 
a corresponding conditional-set machine instruction, that if-conversion 
triggers via `noce_try_addcc' at `-mbranch-cost=3' setting, which makes 
branchless code sequences emitted by if-conversion cheaper than their 
original branched equivalents, and that extraneous instructions such as 
SNEZ, etc. are not present in output.

The reason to XFAIL SImode tests for RV64 targets is the compiler thinks
it has to sign-extend addends, which causes if-conversion to give up.

	gcc/testsuite/
	* gcc.target/riscv/adddifeq.c: New test.
	* gcc.target/riscv/adddifge.c: New test.
	* gcc.target/riscv/adddifgt.c: New test.
	* gcc.target/riscv/adddifle.c: New test.
	* gcc.target/riscv/adddiflt.c: New test.
	* gcc.target/riscv/addsifeq.c: New test.
	* gcc.target/riscv/addsifge.c: New test.
	* gcc.target/riscv/addsifgt.c: New test.
	* gcc.target/riscv/addsifle.c: New test.
	* gcc.target/riscv/addsiflt.c: New test.
---
 gcc/testsuite/gcc.target/riscv/adddifeq.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddifge.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddifgt.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddifle.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddiflt.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsifeq.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsifge.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsifgt.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsifle.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsiflt.c |   26 ++++++++++++++++++++++++++
 10 files changed, 260 insertions(+)

gcc-riscv-test-addccf-generic.diff

Comments

Jeff Law Nov. 19, 2023, 7:47 p.m. UTC | #1 
On 11/18/23 22:43, Maciej W. Rozycki wrote:
> Verify, for generic floating-point conditional-add operations that have
> a corresponding conditional-set machine instruction, that if-conversion
> triggers via `noce_try_addcc' at `-mbranch-cost=3' setting, which makes
> branchless code sequences emitted by if-conversion cheaper than their
> original branched equivalents, and that extraneous instructions such as
> SNEZ, etc. are not present in output.
> 
> The reason to XFAIL SImode tests for RV64 targets is the compiler thinks
> it has to sign-extend addends, which causes if-conversion to give up.
> 
> 	gcc/testsuite/
> 	* gcc.target/riscv/adddifeq.c: New test.
> 	* gcc.target/riscv/adddifge.c: New test.
> 	* gcc.target/riscv/adddifgt.c: New test.
> 	* gcc.target/riscv/adddifle.c: New test.
> 	* gcc.target/riscv/adddiflt.c: New test.
> 	* gcc.target/riscv/addsifeq.c: New test.
> 	* gcc.target/riscv/addsifge.c: New test.
> 	* gcc.target/riscv/addsifgt.c: New test.
> 	* gcc.target/riscv/addsifle.c: New test.
> 	* gcc.target/riscv/addsiflt.c: New test.
OK
jeff
diff mbox series

Patch

Index: gcc/gcc/testsuite/gcc.target/riscv/adddifeq.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/adddifeq.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a5,a5,a1
+	add	a0,a5,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/adddifge.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/adddifge.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddifge (double w, double x, int_t y, int_t z)
+{
+  return w >= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	fge.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a5,a5,a1
+	add	a0,a5,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/adddifgt.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/adddifgt.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddifgt (double w, double x, int_t y, int_t z)
+{
+  return w > x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	fgt.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a5,a5,a1
+	add	a0,a5,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/adddifle.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/adddifle.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddifle (double w, double x, int_t y, int_t z)
+{
+  return w <= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	fle.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a5,a5,a1
+	add	a0,a5,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/adddiflt.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/adddiflt.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddiflt (double w, double x, int_t y, int_t z)
+{
+  return w < x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	flt.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a5,a5,a1
+	add	a0,a5,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/addsifeq.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/addsifeq.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	neg[w]	a5,a5
+	and	a5,a5,a1
+	add[w]	a0,a5,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/addsifge.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/addsifge.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsifge (double w, double x, int_t y, int_t z)
+{
+  return w >= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	fge.d	a5,fa0,fa1
+	neg[w]	a5,a5
+	and	a5,a5,a1
+	add[w]	a0,a5,a0
+ */
+
+/* { /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/addsifgt.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/addsifgt.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsifgt (double w, double x, int_t y, int_t z)
+{
+  return w > x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	fgt.d	a5,fa0,fa1
+	neg[w]	a5,a5
+	and	a5,a5,a1
+	add[w]	a0,a5,a0
+ */
+
+/* { /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/addsifle.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/addsifle.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsifle (double w, double x, int_t y, int_t z)
+{
+  return w <= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	fle.d	a5,fa0,fa1
+	neg[w]	a5,a5
+	and	a5,a5,a1
+	add[w]	a0,a5,a0
+ */
+
+/* { /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/addsiflt.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/addsiflt.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsiflt (double w, double x, int_t y, int_t z)
+{
+  return w < x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	flt.d	a5,fa0,fa1
+	neg[w]	a5,a5
+	and	a5,a5,a1
+	add[w]	a0,a5,a0
+ */
+
+/* { /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */