[10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations

Verify, for T-Head, Ventana and Zicond targets and the integer 
conditional-move operations that already work as expected, that 
if-conversion does *not* trigger at the respective sufficiently low 
`-mbranch-cost=' settings that make original branched code sequences 
cheaper than their branchless equivalents if-conversion would emit.  
Cover all integer relational operations to make sure no corner case 
escapes.

The reason to XFAIL movdibne-thead.c and movsibne-thead.c is the 
branchless T-Head sequence:

	sub	a1,a0,a1
	th.mveqz	a2,a3,a1
	mv	a0,a2
	ret

produced rather than its original branched counterpart:

	beq	a0,a1,.L3
	mv	a0,a2
	ret
.L3:
	mv	a0,a3
	ret

at `-mbranch-cost=1', even though under this setting the latter sequence 
is obviously cheaper performance-wise.  This is because the final move 
instruction in the branchless sequence is not counted towards its cost 
and consequently the cost of both sequences works out at 8 each, making 
if-conversion prefer the branchless variant.  Use the XFAIL mark to keep 
track of these cases for future consideration.

	gcc/testsuite/
	* gcc.target/riscv/movdibeq-thead.c: New test.
	* gcc.target/riscv/movdibge-ventana.c: New test.
	* gcc.target/riscv/movdibge-zicond.c: New test.
	* gcc.target/riscv/movdibgeu-ventana.c: New test.
	* gcc.target/riscv/movdibgeu-zicond.c: New test.
	* gcc.target/riscv/movdibgt-ventana.c: New test.
	* gcc.target/riscv/movdibgt-zicond.c: New test.
	* gcc.target/riscv/movdible-ventana.c: New test.
	* gcc.target/riscv/movdible-zicond.c: New test.
	* gcc.target/riscv/movdibleu-ventana.c: New test.
	* gcc.target/riscv/movdibleu-zicond.c: New test.
	* gcc.target/riscv/movdiblt-ventana.c: New test.
	* gcc.target/riscv/movdiblt-zicond.c: New test.
	* gcc.target/riscv/movdibne-thead.c: New test.
	* gcc.target/riscv/movsibeq-thead.c: New test.
	* gcc.target/riscv/movsibge-ventana.c: New test.
	* gcc.target/riscv/movsibge-zicond.c: New test.
	* gcc.target/riscv/movsibgeu-ventana.c: New test.
	* gcc.target/riscv/movsibgeu-zicond.c: New test.
	* gcc.target/riscv/movsibgt-ventana.c: New test.
	* gcc.target/riscv/movsibgt-zicond.c: New test.
	* gcc.target/riscv/movsible-ventana.c: New test.
	* gcc.target/riscv/movsible-zicond.c: New test.
	* gcc.target/riscv/movsibleu-ventana.c: New test.
	* gcc.target/riscv/movsibleu-zicond.c: New test.
	* gcc.target/riscv/movsiblt-ventana.c: New test.
	* gcc.target/riscv/movsiblt-zicond.c: New test.
	* gcc.target/riscv/movsibne-thead.c: New test.
---
 gcc/testsuite/gcc.target/riscv/movdibeq-thead.c    |   27 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibge-ventana.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibge-zicond.c   |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibgeu-zicond.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibgt-zicond.c   |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdible-ventana.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdible-zicond.c   |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibleu-zicond.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdiblt-zicond.c   |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibne-thead.c    |   29 +++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibeq-thead.c    |   27 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibge-ventana.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibge-zicond.c   |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibgeu-zicond.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibgt-zicond.c   |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsible-ventana.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsible-zicond.c   |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibleu-zicond.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c  |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsiblt-zicond.c   |   28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibne-thead.c    |   29 +++++++++++++++++++++
 28 files changed, 784 insertions(+)

gcc-riscv-branch-cost-test-movcc-branch.diff

LGTM, thanks for those test cases!

On Sun, Nov 19, 2023 at 1:37 PM Maciej W. Rozycki <macro@embecosm.com> wrote:
>
> Verify, for T-Head, Ventana and Zicond targets and the integer
> conditional-move operations that already work as expected, that
> if-conversion does *not* trigger at the respective sufficiently low
> `-mbranch-cost=' settings that make original branched code sequences
> cheaper than their branchless equivalents if-conversion would emit.
> Cover all integer relational operations to make sure no corner case
> escapes.
>
> The reason to XFAIL movdibne-thead.c and movsibne-thead.c is the
> branchless T-Head sequence:
>
>         sub     a1,a0,a1
>         th.mveqz        a2,a3,a1
>         mv      a0,a2
>         ret
>
> produced rather than its original branched counterpart:
>
>         beq     a0,a1,.L3
>         mv      a0,a2
>         ret
> .L3:
>         mv      a0,a3
>         ret
>
> at `-mbranch-cost=1', even though under this setting the latter sequence
> is obviously cheaper performance-wise.  This is because the final move
> instruction in the branchless sequence is not counted towards its cost
> and consequently the cost of both sequences works out at 8 each, making
> if-conversion prefer the branchless variant.  Use the XFAIL mark to keep
> track of these cases for future consideration.
>
>         gcc/testsuite/
>         * gcc.target/riscv/movdibeq-thead.c: New test.
>         * gcc.target/riscv/movdibge-ventana.c: New test.
>         * gcc.target/riscv/movdibge-zicond.c: New test.
>         * gcc.target/riscv/movdibgeu-ventana.c: New test.
>         * gcc.target/riscv/movdibgeu-zicond.c: New test.
>         * gcc.target/riscv/movdibgt-ventana.c: New test.
>         * gcc.target/riscv/movdibgt-zicond.c: New test.
>         * gcc.target/riscv/movdible-ventana.c: New test.
>         * gcc.target/riscv/movdible-zicond.c: New test.
>         * gcc.target/riscv/movdibleu-ventana.c: New test.
>         * gcc.target/riscv/movdibleu-zicond.c: New test.
>         * gcc.target/riscv/movdiblt-ventana.c: New test.
>         * gcc.target/riscv/movdiblt-zicond.c: New test.
>         * gcc.target/riscv/movdibne-thead.c: New test.
>         * gcc.target/riscv/movsibeq-thead.c: New test.
>         * gcc.target/riscv/movsibge-ventana.c: New test.
>         * gcc.target/riscv/movsibge-zicond.c: New test.
>         * gcc.target/riscv/movsibgeu-ventana.c: New test.
>         * gcc.target/riscv/movsibgeu-zicond.c: New test.
>         * gcc.target/riscv/movsibgt-ventana.c: New test.
>         * gcc.target/riscv/movsibgt-zicond.c: New test.
>         * gcc.target/riscv/movsible-ventana.c: New test.
>         * gcc.target/riscv/movsible-zicond.c: New test.
>         * gcc.target/riscv/movsibleu-ventana.c: New test.
>         * gcc.target/riscv/movsibleu-zicond.c: New test.
>         * gcc.target/riscv/movsiblt-ventana.c: New test.
>         * gcc.target/riscv/movsiblt-zicond.c: New test.
>         * gcc.target/riscv/movsibne-thead.c: New test.
> ---
>  gcc/testsuite/gcc.target/riscv/movdibeq-thead.c    |   27 +++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibge-ventana.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibge-zicond.c   |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibgeu-zicond.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibgt-zicond.c   |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdible-ventana.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdible-zicond.c   |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibleu-zicond.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdiblt-zicond.c   |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movdibne-thead.c    |   29 +++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibeq-thead.c    |   27 +++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibge-ventana.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibge-zicond.c   |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibgeu-zicond.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibgt-zicond.c   |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsible-ventana.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsible-zicond.c   |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibleu-zicond.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c  |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsiblt-zicond.c   |   28 ++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/movsibne-thead.c    |   29 +++++++++++++++++++++
>  28 files changed, 784 insertions(+)
>
> gcc-riscv-branch-cost-test-movcc-branch.diff
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibeq-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibeq-thead.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdieq (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w == x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bne     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:th\\.mveqz|th\\.mvnez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibge-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibge-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdige (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       blt     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibge-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibge-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdige (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       blt     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bltu    a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibgeu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibgeu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bltu    a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigt (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w > x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       ble     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibgt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibgt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigt (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w > x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       ble     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdible-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdible-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdile (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bgt     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdible-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdible-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdile (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bgt     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdileu (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bgtu    a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibleu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibleu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdileu (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bgtu    a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdilt (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w < x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bge     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdiblt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdiblt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdilt (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w < x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bge     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibne-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibne-thead.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdine (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w != x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       beq     a0,a1,.L3
> +       mv      a0,a2
> +       ret
> +.L3:
> +       mv      a0,a3
> +       ret
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\ssub\\s" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\s(?:th\\.mveqz|th\\.mvnez)\\s" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibeq-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibeq-thead.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsieq (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w == x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bne     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:th\\.mveqz|th\\.mvnez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibge-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibge-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsige (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       blt     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibge-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibge-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsige (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       blt     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bltu    a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibgeu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibgeu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bltu    a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigt (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w > x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       ble     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibgt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibgt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigt (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w > x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       ble     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsible-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsible-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsile (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bgt     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsible-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsible-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsile (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bgt     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsileu (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bgtu    a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibleu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibleu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsileu (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bgtu    a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsilt (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w < x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bge     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsiblt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsiblt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsilt (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w < x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       bge     a0,a1,.L2
> +       mv      a3,a2
> +.L2:
> +       mv      a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibne-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibne-thead.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsine (int_t w, int_t x, int_t y, int_t z)
> +{
> +  return w != x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> +       beq     a0,a1,.L3
> +       mv      a0,a2
> +       ret
> +.L3:
> +       mv      a0,a3
> +       ret
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\ssub\\s" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\s(?:th\\.mveqz|th\\.mvnez)\\s" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */