| Message ID | alpine.DEB.2.20.2311181804140.5892@tpp.orcam.me.uk |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Various if-conversion fixes and improvements | expand |
On 11/18/23 22:39, Maciej W. Rozycki wrote: > There is no need for the requirement for conditional-move data input > operands to be stricter for T-Head targets than for short forward branch > targets and limit them to registers only. They are keyed according to > the `sfb_alu_operand' predicate, which lets certain constants through. > Such constants are already forced into a register for the `cons' operand > in the analogous short forward branch case and we can force them for the > `alt' operand and T-Head as well. This enables more opportunities for a > branchless sequence to be produced. > > gcc/ > * config/riscv/riscv.cc (riscv_expand_conditional_move): Also > accept constants for T-Head data input operands. OK. Jeff
Index: gcc/gcc/config/riscv/riscv.cc =================================================================== --- gcc.orig/gcc/config/riscv/riscv.cc +++ gcc/gcc/config/riscv/riscv.cc @@ -4094,8 +4094,6 @@ riscv_expand_conditional_move (rtx dest, if (TARGET_XTHEADCONDMOV && GET_MODE_CLASS (mode) == MODE_INT - && reg_or_0_operand (cons, mode) - && reg_or_0_operand (alt, mode) && (GET_MODE (op) == mode || GET_MODE (op) == E_VOIDmode) && (GET_MODE (op0) == mode || CONST_INT_P (op0)) && (GET_MODE (op1) == mode || CONST_INT_P (op1)) @@ -4113,6 +4111,8 @@ riscv_expand_conditional_move (rtx dest, cases for extensions which are more general than SFB. But does mean we need to force CONS into a register at this point. */ cons = force_reg (mode, cons); + /* With XTheadCondMov we need to force ALT into a register too. */ + alt = force_reg (mode, alt); emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, cons, alt))); return true;
There is no need for the requirement for conditional-move data input operands to be stricter for T-Head targets than for short forward branch targets and limit them to registers only. They are keyed according to the `sfb_alu_operand' predicate, which lets certain constants through. Such constants are already forced into a register for the `cons' operand in the analogous short forward branch case and we can force them for the `alt' operand and T-Head as well. This enables more opportunities for a branchless sequence to be produced. gcc/ * config/riscv/riscv.cc (riscv_expand_conditional_move): Also accept constants for T-Head data input operands. --- gcc/config/riscv/riscv.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) gcc-riscv-expand-conditional-move-thead-alt.diff