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[32/44] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc'

Message ID alpine.DEB.2.20.2311182127160.5892@tpp.orcam.me.uk
State New
Headers show
Series RISC-V: Various if-conversion fixes and improvements | expand

Commit Message

Maciej W. Rozycki Nov. 19, 2023, 5:42 a.m. UTC 
A subsequent change to enable the processing of conditional moves on a 
floating-point condition by `riscv_expand_conditional_move' will cause 
`riscv_expand_float_scc' to be called for word-mode target RTX with RV64 
targets.  In that case an invalid insn such as:

(insn 25 24 0 (set (reg:DI 141)
        (subreg:SI (reg:DI 143) 0)) -1
     (nil))

would be produced, which would crash the compiler later on.  Since the 
output operand of the SET operation to be produced already has the same 
mode as the input operand does, just omit the use of SUBREG and assign 
directly.

	gcc/
	* config/riscv/riscv.cc (riscv_expand_float_scc): Suppress the 
	use of SUBREG if the conditional-set target is word-mode.
---
 gcc/config/riscv/riscv.cc |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

gcc-riscv-expand-float-scc-subreg.diff

Comments

Jeff Law Nov. 19, 2023, 6:26 p.m. UTC | #1 
On 11/18/23 22:42, Maciej W. Rozycki wrote:
> A subsequent change to enable the processing of conditional moves on a
> floating-point condition by `riscv_expand_conditional_move' will cause
> `riscv_expand_float_scc' to be called for word-mode target RTX with RV64
> targets.  In that case an invalid insn such as:
> 
> (insn 25 24 0 (set (reg:DI 141)
>          (subreg:SI (reg:DI 143) 0)) -1
>       (nil))
> 
> would be produced, which would crash the compiler later on.  Since the
> output operand of the SET operation to be produced already has the same
> mode as the input operand does, just omit the use of SUBREG and assign
> directly.
> 
> 	gcc/
> 	* config/riscv/riscv.cc (riscv_expand_float_scc): Suppress the
> 	use of SUBREG if the conditional-set target is word-mode.
OK
jeff
diff mbox series

Patch

Index: gcc/gcc/config/riscv/riscv.cc
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.cc
+++ gcc/gcc/config/riscv/riscv.cc
@@ -4071,7 +4071,9 @@  riscv_expand_float_scc (rtx target, enum
   riscv_emit_float_compare (&code, &op0, &op1);
 
   rtx cmp = riscv_force_binary (word_mode, code, op0, op1);
-  riscv_emit_set (target, lowpart_subreg (SImode, cmp, word_mode));
+  if (GET_MODE (target) != word_mode)
+    cmp = lowpart_subreg (GET_MODE (target), cmp, word_mode);
+  riscv_emit_set (target, cmp);
 }
 
 /* Jump to LABEL if (CODE OP0 OP1) holds.  */