diff mbox series

[34/44] RISC-V: Provide FP conditional-branch instructions for if-conversion

Message ID alpine.DEB.2.20.2311182155320.5892@tpp.orcam.me.uk
State New
Headers show
Series RISC-V: Various if-conversion fixes and improvements | expand

Commit Message

Maciej W. Rozycki Nov. 19, 2023, 5:42 a.m. UTC 
Do not expand floating-point conditional-branch RTL instructions right 
away that use a comparison operation that is either directly available 
as a machine conditional-set instruction or is NE, which can be emulated 
by EQ.  This is so that if-conversion sees them in their original form 
and can produce fewer operations tried in a branchless code sequence 
compared to when such an instruction has been already converted to a 
sequence of a floating-point conditional-set RTL instruction followed by 
an integer conditional-branch RTL instruction.  Split any floating-point 
conditional-branch RTL instructions still remaining after reload then.

Adjust the testsuite accordingly: since the middle end uses the inverse 
condition internally, an inverse conditional-set instruction may make it 
to assembly output and also `cond_move_process_if_block' will be used by 
if-conversion rather than `noce_process_if_block', because the latter 
function not yet been updated to handle inverted conditions.

	gcc/
	* config/riscv/predicates.md (ne_operator): New predicate.
	* config/riscv/riscv.cc (riscv_insn_cost): Handle branches on a 
	floating-point condition.
	* config/riscv/riscv.md (@cbranch<mode>4): Rename expander to...
	(@cbranch<ANYF:mode>4): ... this.  Only expand the RTX via 
	`riscv_expand_conditional_branch' for `!signed_order_operator' 
	operators, otherwise let it through.
	(*cbranch<ANYF:mode>4, *cbranch<ANYF:mode>4): New insns and 
	splitters.

	gcc/testsuite/
	* gcc.target/riscv/movdifge-sfb.c: Reject "if-conversion 
	succeeded through" rather than accepting it.
	* gcc.target/riscv/movdifge-thead.c: Likewise.
	* gcc.target/riscv/movdifge-ventana.c: Likewise.
	* gcc.target/riscv/movdifge-zicond.c: Likewise.
	* gcc.target/riscv/movdifgt-sfb.c: Likewise.
	* gcc.target/riscv/movdifgt-thead.c: Likewise.
	* gcc.target/riscv/movdifgt-ventana.c: Likewise.
	* gcc.target/riscv/movdifgt-zicond.c: Likewise.
	* gcc.target/riscv/movdifle-sfb.c: Likewise.
	* gcc.target/riscv/movdifle-thead.c: Likewise.
	* gcc.target/riscv/movdifle-ventana.c: Likewise.
	* gcc.target/riscv/movdifle-zicond.c: Likewise.
	* gcc.target/riscv/movdiflt-sfb.c: Likewise.
	* gcc.target/riscv/movdiflt-thead.c: Likewise.
	* gcc.target/riscv/movdiflt-ventana.c: Likewise.
	* gcc.target/riscv/movdiflt-zicond.c: Likewise.
	* gcc.target/riscv/movsifge-sfb.c: Likewise.
	* gcc.target/riscv/movsifge-thead.c: Likewise.
	* gcc.target/riscv/movsifge-ventana.c: Likewise.
	* gcc.target/riscv/movsifge-zicond.c: Likewise.
	* gcc.target/riscv/movsifgt-sfb.c: Likewise.
	* gcc.target/riscv/movsifgt-thead.c: Likewise.
	* gcc.target/riscv/movsifgt-ventana.c: Likewise.
	* gcc.target/riscv/movsifgt-zicond.c: Likewise.
	* gcc.target/riscv/movsifle-sfb.c: Likewise.
	* gcc.target/riscv/movsifle-thead.c: Likewise.
	* gcc.target/riscv/movsifle-ventana.c: Likewise.
	* gcc.target/riscv/movsifle-zicond.c: Likewise.
	* gcc.target/riscv/movsiflt-sfb.c: Likewise.
	* gcc.target/riscv/movsiflt-thead.c: Likewise.
	* gcc.target/riscv/movsiflt-ventana.c: Likewise.
	* gcc.target/riscv/movsiflt-zicond.c: Likewise.
	* gcc.target/riscv/smax-ieee.c: Also accept FLT.D.
	* gcc.target/riscv/smaxf-ieee.c: Also accept FLT.S.
	* gcc.target/riscv/smin-ieee.c: Also accept FGT.D.
	* gcc.target/riscv/sminf-ieee.c: Also accept FGT.S.
---
 gcc/config/riscv/predicates.md                    |    3 
 gcc/config/riscv/riscv.cc                         |   22 +++--
 gcc/config/riscv/riscv.md                         |   89 +++++++++++++++++++---
 gcc/testsuite/gcc.target/riscv/movdifge-sfb.c     |    2 
 gcc/testsuite/gcc.target/riscv/movdifge-thead.c   |    2 
 gcc/testsuite/gcc.target/riscv/movdifge-ventana.c |    2 
 gcc/testsuite/gcc.target/riscv/movdifge-zicond.c  |    2 
 gcc/testsuite/gcc.target/riscv/movdifgt-sfb.c     |    2 
 gcc/testsuite/gcc.target/riscv/movdifgt-thead.c   |    2 
 gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c |    2 
 gcc/testsuite/gcc.target/riscv/movdifgt-zicond.c  |    2 
 gcc/testsuite/gcc.target/riscv/movdifle-sfb.c     |    2 
 gcc/testsuite/gcc.target/riscv/movdifle-thead.c   |    2 
 gcc/testsuite/gcc.target/riscv/movdifle-ventana.c |    2 
 gcc/testsuite/gcc.target/riscv/movdifle-zicond.c  |    2 
 gcc/testsuite/gcc.target/riscv/movdiflt-sfb.c     |    2 
 gcc/testsuite/gcc.target/riscv/movdiflt-thead.c   |    2 
 gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c |    2 
 gcc/testsuite/gcc.target/riscv/movdiflt-zicond.c  |    2 
 gcc/testsuite/gcc.target/riscv/movsifge-sfb.c     |    2 
 gcc/testsuite/gcc.target/riscv/movsifge-thead.c   |    2 
 gcc/testsuite/gcc.target/riscv/movsifge-ventana.c |    2 
 gcc/testsuite/gcc.target/riscv/movsifge-zicond.c  |    2 
 gcc/testsuite/gcc.target/riscv/movsifgt-sfb.c     |    2 
 gcc/testsuite/gcc.target/riscv/movsifgt-thead.c   |    2 
 gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c |    2 
 gcc/testsuite/gcc.target/riscv/movsifgt-zicond.c  |    2 
 gcc/testsuite/gcc.target/riscv/movsifle-sfb.c     |    2 
 gcc/testsuite/gcc.target/riscv/movsifle-thead.c   |    2 
 gcc/testsuite/gcc.target/riscv/movsifle-ventana.c |    2 
 gcc/testsuite/gcc.target/riscv/movsifle-zicond.c  |    2 
 gcc/testsuite/gcc.target/riscv/movsiflt-sfb.c     |    2 
 gcc/testsuite/gcc.target/riscv/movsiflt-thead.c   |    2 
 gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c |    2 
 gcc/testsuite/gcc.target/riscv/movsiflt-zicond.c  |    2 
 gcc/testsuite/gcc.target/riscv/smax-ieee.c        |    2 
 gcc/testsuite/gcc.target/riscv/smaxf-ieee.c       |    2 
 gcc/testsuite/gcc.target/riscv/smin-ieee.c        |    2 
 gcc/testsuite/gcc.target/riscv/sminf-ieee.c       |    2 
 39 files changed, 134 insertions(+), 52 deletions(-)

gcc-riscv-cbranch-split.diff

Comments

Jeff Law Nov. 19, 2023, 7:42 p.m. UTC | #1 
On 11/18/23 22:42, Maciej W. Rozycki wrote:
> Do not expand floating-point conditional-branch RTL instructions right
> away that use a comparison operation that is either directly available
> as a machine conditional-set instruction or is NE, which can be emulated
> by EQ.  This is so that if-conversion sees them in their original form
> and can produce fewer operations tried in a branchless code sequence
> compared to when such an instruction has been already converted to a
> sequence of a floating-point conditional-set RTL instruction followed by
> an integer conditional-branch RTL instruction.  Split any floating-point
> conditional-branch RTL instructions still remaining after reload then.
> 
> Adjust the testsuite accordingly: since the middle end uses the inverse
> condition internally, an inverse conditional-set instruction may make it
> to assembly output and also `cond_move_process_if_block' will be used by
> if-conversion rather than `noce_process_if_block', because the latter
> function not yet been updated to handle inverted conditions.
> 
> 	gcc/
> 	* config/riscv/predicates.md (ne_operator): New predicate.
> 	* config/riscv/riscv.cc (riscv_insn_cost): Handle branches on a
> 	floating-point condition.
> 	* config/riscv/riscv.md (@cbranch<mode>4): Rename expander to...
> 	(@cbranch<ANYF:mode>4): ... this.  Only expand the RTX via
> 	`riscv_expand_conditional_branch' for `!signed_order_operator'
> 	operators, otherwise let it through.
> 	(*cbranch<ANYF:mode>4, *cbranch<ANYF:mode>4): New insns and
> 	splitters.
> 
> 	gcc/testsuite/
> 	* gcc.target/riscv/movdifge-sfb.c: Reject "if-conversion
> 	succeeded through" rather than accepting it.
> 	* gcc.target/riscv/movdifge-thead.c: Likewise.
> 	* gcc.target/riscv/movdifge-ventana.c: Likewise.
> 	* gcc.target/riscv/movdifge-zicond.c: Likewise.
> 	* gcc.target/riscv/movdifgt-sfb.c: Likewise.
> 	* gcc.target/riscv/movdifgt-thead.c: Likewise.
> 	* gcc.target/riscv/movdifgt-ventana.c: Likewise.
> 	* gcc.target/riscv/movdifgt-zicond.c: Likewise.
> 	* gcc.target/riscv/movdifle-sfb.c: Likewise.
> 	* gcc.target/riscv/movdifle-thead.c: Likewise.
> 	* gcc.target/riscv/movdifle-ventana.c: Likewise.
> 	* gcc.target/riscv/movdifle-zicond.c: Likewise.
> 	* gcc.target/riscv/movdiflt-sfb.c: Likewise.
> 	* gcc.target/riscv/movdiflt-thead.c: Likewise.
> 	* gcc.target/riscv/movdiflt-ventana.c: Likewise.
> 	* gcc.target/riscv/movdiflt-zicond.c: Likewise.
> 	* gcc.target/riscv/movsifge-sfb.c: Likewise.
> 	* gcc.target/riscv/movsifge-thead.c: Likewise.
> 	* gcc.target/riscv/movsifge-ventana.c: Likewise.
> 	* gcc.target/riscv/movsifge-zicond.c: Likewise.
> 	* gcc.target/riscv/movsifgt-sfb.c: Likewise.
> 	* gcc.target/riscv/movsifgt-thead.c: Likewise.
> 	* gcc.target/riscv/movsifgt-ventana.c: Likewise.
> 	* gcc.target/riscv/movsifgt-zicond.c: Likewise.
> 	* gcc.target/riscv/movsifle-sfb.c: Likewise.
> 	* gcc.target/riscv/movsifle-thead.c: Likewise.
> 	* gcc.target/riscv/movsifle-ventana.c: Likewise.
> 	* gcc.target/riscv/movsifle-zicond.c: Likewise.
> 	* gcc.target/riscv/movsiflt-sfb.c: Likewise.
> 	* gcc.target/riscv/movsiflt-thead.c: Likewise.
> 	* gcc.target/riscv/movsiflt-ventana.c: Likewise.
> 	* gcc.target/riscv/movsiflt-zicond.c: Likewise.
> 	* gcc.target/riscv/smax-ieee.c: Also accept FLT.D.
> 	* gcc.target/riscv/smaxf-ieee.c: Also accept FLT.S.
> 	* gcc.target/riscv/smin-ieee.c: Also accept FGT.D.
> 	* gcc.target/riscv/sminf-ieee.c: Also accept FGT.S.
So this is a more gradual lowering of the FP branches to allow ifcvt to 
do a better job.  Seems generally reasonable.  I don't expect that we're 
missing any significant simplifications, though I probably could 
construct a missed CSE/GCSE if I worked at it for a bit.

Presumably the length computation can't be handled by the generic code 
we've already got in place?

OK for the trunk.

jeff
Maciej W. Rozycki Nov. 23, 2023, 11:26 p.m. UTC | #2 
On Sun, 19 Nov 2023, Jeff Law wrote:

> So this is a more gradual lowering of the FP branches to allow ifcvt to do a
> better job.  Seems generally reasonable.  I don't expect that we're missing
> any significant simplifications, though I probably could construct a missed
> CSE/GCSE if I worked at it for a bit.

 I've been thinking about it a little before submitting this patch in its 
final form.  I considered activating the splitter in split1 rather than 
split2, but figured out it would likely make little if any difference.  
We could add another, yet earlier split pass I suppose, somewhere between 
ce1 and cse2.  I'm not sure it would be worth it though.

> Presumably the length computation can't be handled by the generic code we've
> already got in place?

 I disregarded such an option right away at the time of writing this code. 
I'm sure this code could be folded, but not in a straightforward way.  
Notice the different, misaligned branch spans, owing to the machine branch 
instruction being the second in the ultimate instruction pair produced.  
So getting rid of this extra code may not be worth the complication in the 
common "length" attribute value calculation unless, perhaps, we factor the 
branch case out to a C++ function.

  Maciej
diff mbox series

Patch

Index: gcc/gcc/config/riscv/predicates.md
===================================================================
--- gcc.orig/gcc/config/riscv/predicates.md
+++ gcc/gcc/config/riscv/predicates.md
@@ -333,6 +333,9 @@ 
 (define_predicate "modular_operator"
   (match_code "plus,minus,mult,ashift"))
 
+(define_predicate "ne_operator"
+  (match_code "ne"))
+
 (define_predicate "equality_operator"
   (match_code "eq,ne"))
 
Index: gcc/gcc/config/riscv/riscv.cc
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.cc
+++ gcc/gcc/config/riscv/riscv.cc
@@ -3308,7 +3308,9 @@  riscv_address_cost (rtx addr, machine_mo
    calculation for conditional branches: one unit is considered the cost
    of microarchitecture-dependent actual branch execution and therefore
    multiplied by BRANCH_COST and any remaining units are considered fixed
-   branch overhead.  */
+   branch overhead.  Branches on a floating-point condition incur an extra
+   instruction cost as they will be split into an FCMP operation followed
+   by a branch on an integer condition.  */
 
 static int
 riscv_insn_cost (rtx_insn *insn, bool speed)
@@ -3316,11 +3318,19 @@  riscv_insn_cost (rtx_insn *insn, bool sp
   rtx x = PATTERN (insn);
   int cost = pattern_cost (x, speed);
 
-  if (JUMP_P (insn)
-      && GET_CODE (x) == SET
-      && GET_CODE (SET_DEST (x)) == PC
-      && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE)
-    cost += COSTS_N_INSNS (BRANCH_COST (speed, false) - 1);
+  if (JUMP_P (insn))
+    {
+      if (GET_CODE (x) == PARALLEL)
+	x = XVECEXP (x, 0, 0);
+      if (GET_CODE (x) == SET
+	  && GET_CODE (SET_DEST (x)) == PC
+	  && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE)
+	{
+	  cost += COSTS_N_INSNS (BRANCH_COST (speed, false) - 1);
+	  if (FLOAT_MODE_P (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
+	    cost += COSTS_N_INSNS (1);
+	}
+    }
   return cost;
 }
 
Index: gcc/gcc/config/riscv/riscv.md
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.md
+++ gcc/gcc/config/riscv/riscv.md
@@ -2750,20 +2750,89 @@ 
   DONE;
 })
 
-(define_expand "@cbranch<mode>4"
-  [(set (pc)
-	(if_then_else (match_operator 0 "fp_branch_comparison"
-		       [(match_operand:ANYF 1 "register_operand")
-			(match_operand:ANYF 2 "register_operand")])
-		      (label_ref (match_operand 3 ""))
-		      (pc)))]
+(define_expand "@cbranch<ANYF:mode>4"
+  [(parallel [(set (pc)
+		   (if_then_else (match_operator 0 "fp_branch_comparison"
+				  [(match_operand:ANYF 1 "register_operand")
+				   (match_operand:ANYF 2 "register_operand")])
+				 (label_ref (match_operand 3 ""))
+				 (pc)))
+	      (clobber (match_operand 4 ""))])]
   "TARGET_HARD_FLOAT || TARGET_ZFINX"
 {
-  riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
-				   operands[1], operands[2]);
-  DONE;
+  if (!signed_order_operator (operands[0], GET_MODE (operands[0])))
+    {
+      riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
+				       operands[1], operands[2]);
+      DONE;
+    }
+  operands[4] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
 })
 
+(define_insn_and_split "*cbranch<ANYF:mode>4"
+  [(set (pc)
+	(if_then_else (match_operator 1 "fp_native_comparison"
+		       [(match_operand:ANYF 2 "register_operand" "f")
+			(match_operand:ANYF 3 "register_operand" "f")])
+		      (label_ref (match_operand 0 ""))
+		      (pc)))
+   (clobber (match_operand:X 4 "register_operand" "=r"))]
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 4)
+	(match_op_dup:X 1 [(match_dup 2) (match_dup 3)]))
+   (set (pc)
+        (if_then_else (ne:X (match_dup 4) (const_int 0))
+		      (label_ref (match_operand 0))
+		      (pc)))]
+  ""
+  [(set_attr "type" "branch")
+   (set (attr "length")
+	(if_then_else (and (le (minus (match_dup 0) (pc))
+			       (const_int 4084))
+			   (le (minus (pc) (match_dup 0))
+			       (const_int 4096)))
+		      (const_int 8)
+		      (if_then_else (and (le (minus (match_dup 0) (pc))
+					     (const_int 1048564))
+					 (le (minus (pc) (match_dup 0))
+					     (const_int 1048576)))
+				    (const_int 12)
+				    (const_int 16))))])
+
+(define_insn_and_split "*cbranch<ANYF:mode>4"
+  [(set (pc)
+	(if_then_else (match_operator 1 "ne_operator"
+		       [(match_operand:ANYF 2 "register_operand" "f")
+			(match_operand:ANYF 3 "register_operand" "f")])
+		      (label_ref (match_operand 0 ""))
+		      (pc)))
+   (clobber (match_operand:X 4 "register_operand" "=r"))]
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 4)
+	(eq:X (match_dup 2) (match_dup 3)))
+   (set (pc)
+        (if_then_else (eq:X (match_dup 4) (const_int 0))
+		      (label_ref (match_operand 0))
+		      (pc)))]
+  ""
+  [(set_attr "type" "branch")
+   (set (attr "length")
+	(if_then_else (and (le (minus (match_dup 0) (pc))
+			       (const_int 4084))
+			   (le (minus (pc) (match_dup 0))
+			       (const_int 4096)))
+		      (const_int 8)
+		      (if_then_else (and (le (minus (match_dup 0) (pc))
+					     (const_int 1048564))
+					 (le (minus (pc) (match_dup 0))
+					     (const_int 1048576)))
+				    (const_int 12)
+				    (const_int 16))))])
+
 (define_insn_and_split "*branch_on_bit<X:mode>"
   [(set (pc)
 	(if_then_else
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifge-sfb.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifge-sfb.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifge-sfb.c
@@ -20,7 +20,7 @@  movdifge (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifge-thead.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifge-thead.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifge-thead.c
@@ -18,7 +18,7 @@  movdifge (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifge-ventana.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifge-ventana.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifge-ventana.c
@@ -20,7 +20,7 @@  movdifge (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifge-zicond.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifge-zicond.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifge-zicond.c
@@ -20,7 +20,7 @@  movdifge (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifgt-sfb.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifgt-sfb.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifgt-sfb.c
@@ -20,7 +20,7 @@  movdifgt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifgt-thead.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifgt-thead.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifgt-thead.c
@@ -18,7 +18,7 @@  movdifgt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c
@@ -20,7 +20,7 @@  movdifgt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifgt-zicond.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifgt-zicond.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifgt-zicond.c
@@ -20,7 +20,7 @@  movdifgt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifle-sfb.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifle-sfb.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifle-sfb.c
@@ -20,7 +20,7 @@  movdifle (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifle-thead.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifle-thead.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifle-thead.c
@@ -18,7 +18,7 @@  movdifle (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifle-ventana.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifle-ventana.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifle-ventana.c
@@ -20,7 +20,7 @@  movdifle (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdifle-zicond.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdifle-zicond.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdifle-zicond.c
@@ -20,7 +20,7 @@  movdifle (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdiflt-sfb.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdiflt-sfb.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdiflt-sfb.c
@@ -20,7 +20,7 @@  movdiflt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdiflt-thead.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdiflt-thead.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdiflt-thead.c
@@ -18,7 +18,7 @@  movdiflt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c
@@ -20,7 +20,7 @@  movdiflt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdiflt-zicond.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movdiflt-zicond.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movdiflt-zicond.c
@@ -20,7 +20,7 @@  movdiflt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifge-sfb.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifge-sfb.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifge-sfb.c
@@ -20,7 +20,7 @@  movsifge (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifge-thead.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifge-thead.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifge-thead.c
@@ -18,7 +18,7 @@  movsifge (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifge-ventana.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifge-ventana.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifge-ventana.c
@@ -20,7 +20,7 @@  movsifge (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifge-zicond.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifge-zicond.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifge-zicond.c
@@ -20,7 +20,7 @@  movsifge (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifgt-sfb.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifgt-sfb.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifgt-sfb.c
@@ -20,7 +20,7 @@  movsifgt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifgt-thead.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifgt-thead.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifgt-thead.c
@@ -18,7 +18,7 @@  movsifgt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c
@@ -20,7 +20,7 @@  movsifgt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifgt-zicond.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifgt-zicond.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifgt-zicond.c
@@ -20,7 +20,7 @@  movsifgt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifle-sfb.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifle-sfb.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifle-sfb.c
@@ -20,7 +20,7 @@  movsifle (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifle-thead.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifle-thead.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifle-thead.c
@@ -18,7 +18,7 @@  movsifle (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifle-ventana.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifle-ventana.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifle-ventana.c
@@ -20,7 +20,7 @@  movsifle (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsifle-zicond.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsifle-zicond.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsifle-zicond.c
@@ -20,7 +20,7 @@  movsifle (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsiflt-sfb.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsiflt-sfb.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsiflt-sfb.c
@@ -20,7 +20,7 @@  movsiflt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsiflt-thead.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsiflt-thead.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsiflt-thead.c
@@ -18,7 +18,7 @@  movsiflt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
 /* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c
@@ -20,7 +20,7 @@  movsiflt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsiflt-zicond.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/movsiflt-zicond.c
+++ gcc/gcc/testsuite/gcc.target/riscv/movsiflt-zicond.c
@@ -20,7 +20,7 @@  movsiflt (double w, double x, int_t y, i
  */
 
 /* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
-/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
 /* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
 /* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/smax-ieee.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/smax-ieee.c
+++ gcc/gcc/testsuite/gcc.target/riscv/smax-ieee.c
@@ -10,4 +10,4 @@  smax (double x, double y)
 
 /* { dg-final { scan-assembler-not "\t(call|tail)\tfmax\t" } } */
 /* { dg-final { scan-assembler-not "\tfmax\\.d\t" } } */
-/* { dg-final { scan-assembler "\tfge\\.d\t" } } */
+/* { dg-final { scan-assembler "\t(fge\\.d|flt\\.d)\t" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/smaxf-ieee.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/smaxf-ieee.c
+++ gcc/gcc/testsuite/gcc.target/riscv/smaxf-ieee.c
@@ -10,4 +10,4 @@  smaxf (float x, float y)
 
 /* { dg-final { scan-assembler-not "\t(call|tail)\tfmaxf\t" } } */
 /* { dg-final { scan-assembler-not "\tfmax\\.s\t" } } */
-/* { dg-final { scan-assembler "\tfge\\.s\t" } } */
+/* { dg-final { scan-assembler "\t(fge\\.s|flt\\.s)\t" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/smin-ieee.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/smin-ieee.c
+++ gcc/gcc/testsuite/gcc.target/riscv/smin-ieee.c
@@ -10,4 +10,4 @@  smin (double x, double y)
 
 /* { dg-final { scan-assembler-not "\t(call|tail)\tfmin\t" } } */
 /* { dg-final { scan-assembler-not "\tfmin\\.d\t" } } */
-/* { dg-final { scan-assembler "\tfle\\.d\t" } } */
+/* { dg-final { scan-assembler "\t(fgt\\.d|fle\\.d)\t" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/sminf-ieee.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/sminf-ieee.c
+++ gcc/gcc/testsuite/gcc.target/riscv/sminf-ieee.c
@@ -10,4 +10,4 @@  sminf (float x, float y)
 
 /* { dg-final { scan-assembler-not "\t(call|tail)\tfminf\t" } } */
 /* { dg-final { scan-assembler-not "\tfmin\\.s\t" } } */
-/* { dg-final { scan-assembler "\tfle\\.s\t" } } */
+/* { dg-final { scan-assembler "\t(fgt\\.s|fle\\.s)\t" } } */