| Message ID | alpine.DEB.2.20.2311171632580.5892@tpp.orcam.me.uk |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Various if-conversion fixes and improvements | expand |
LGTM On Sun, Nov 19, 2023 at 1:38 PM Maciej W. Rozycki <macro@embecosm.com> wrote: > > Verify, for Ventana and Zicond targets and the ordered floating-point > conditional-move operations that already work as expected, that > if-conversion does *not* trigger at `-mbranch-cost=2' setting, which > makes original branched code sequences cheaper than their branchless > equivalents if-conversion would emit. Cover all ordered floating-point > relational operations to make sure no corner case escapes. > > gcc/testsuite/ > * gcc.target/riscv/movdibfge-ventana.c: New test. > * gcc.target/riscv/movdibfge-zicond.c: New test. > * gcc.target/riscv/movdibfgt-ventana.c: New test. > * gcc.target/riscv/movdibfgt-zicond.c: New test. > * gcc.target/riscv/movdibfle-ventana.c: New test. > * gcc.target/riscv/movdibfle-zicond.c: New test. > * gcc.target/riscv/movdibflt-ventana.c: New test. > * gcc.target/riscv/movdibflt-zicond.c: New test. > * gcc.target/riscv/movdibfne-ventana.c: New test. > * gcc.target/riscv/movdibfne-zicond.c: New test. > * gcc.target/riscv/movsibfge-ventana.c: New test. > * gcc.target/riscv/movsibfge-zicond.c: New test. > * gcc.target/riscv/movsibfgt-ventana.c: New test. > * gcc.target/riscv/movsibfgt-zicond.c: New test. > * gcc.target/riscv/movsibfle-ventana.c: New test. > * gcc.target/riscv/movsibfle-zicond.c: New test. > * gcc.target/riscv/movsibflt-ventana.c: New test. > * gcc.target/riscv/movsibflt-zicond.c: New test. > * gcc.target/riscv/movsibfne-ventana.c: New test. > * gcc.target/riscv/movsibfne-zicond.c: New test. > --- > gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c | 29 ++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c | 29 ++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c | 30 +++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c | 30 +++++++++++++++++++++ > 20 files changed, 598 insertions(+) > > gcc-riscv-branch-cost-test-movccf-branch.diff > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifge (double w, double x, int_t y, int_t z) > +{ > + return w >= x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fge.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifge (double w, double x, int_t y, int_t z) > +{ > + return w >= x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fge.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifgt (double w, double x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fgt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifgt (double w, double x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fgt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifle (double w, double x, int_t y, int_t z) > +{ > + return w <= x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fle.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifle (double w, double x, int_t y, int_t z) > +{ > + return w <= x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fle.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdiflt (double w, double x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + flt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdiflt (double w, double x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + flt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifne (double w, double x, int_t y, int_t z) > +{ > + return w != x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + feq.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + bne a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifne (double w, double x, int_t y, int_t z) > +{ > + return w != x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + feq.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + bne a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifge (double w, double x, int_t y, int_t z) > +{ > + return w >= x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fge.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifge (double w, double x, int_t y, int_t z) > +{ > + return w >= x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fge.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifgt (double w, double x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fgt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifgt (double w, double x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fgt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifle (double w, double x, int_t y, int_t z) > +{ > + return w <= x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fle.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifle (double w, double x, int_t y, int_t z) > +{ > + return w <= x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fle.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsiflt (double w, double x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + flt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsiflt (double w, double x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + flt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifne (double w, double x, int_t y, int_t z) > +{ > + return w != x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + feq.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + bne a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c > =================================================================== > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifne (double w, double x, int_t y, int_t z) > +{ > + return w != x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + feq.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + bne a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branched assembly like: + + fge.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branched assembly like: + + fge.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branched assembly like: + + fgt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branched assembly like: + + fgt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branched assembly like: + + fle.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branched assembly like: + + fle.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branched assembly like: + + flt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branched assembly like: + + flt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + feq.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + bne a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + feq.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + bne a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branched assembly like: + + fge.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branched assembly like: + + fge.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branched assembly like: + + fgt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branched assembly like: + + fgt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branched assembly like: + + fle.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branched assembly like: + + fle.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branched assembly like: + + flt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branched assembly like: + + flt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + feq.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + bne a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + feq.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + bne a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */