[28/44] RISC-V/testsuite: Add branchless cases for generic integer cond moves

Message ID	alpine.DEB.2.20.2311182049270.5892@tpp.orcam.me.uk
State	New
Headers	show Return-Path: <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DEB8A3857C7E Date: Sun, 19 Nov 2023 05:41:12 +0000 (GMT) From: "Maciej W. Rozycki" <macro@embecosm.com> To: gcc-patches@gcc.gnu.org cc: Andrew Waterman <andrew@sifive.com>, Jim Wilson <jim.wilson.gcc@gmail.com>, Kito Cheng <kito.cheng@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: [PATCH 28/44] RISC-V/testsuite: Add branchless cases for generic integer cond moves In-Reply-To: <alpine.DEB.2.20.2311171315580.5892@tpp.orcam.me.uk> Message-ID: <alpine.DEB.2.20.2311182049270.5892@tpp.orcam.me.uk> References: <alpine.DEB.2.20.2311171315580.5892@tpp.orcam.me.uk> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Precedence: list Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	RISC-V: Various if-conversion fixes and improvements \| expand [00/44] RISC-V: Various if-conversion fixes and improvements [13/44] RISC-V/testsuite: Add branchless cases for FP cond-move operations [01/44] testsuite: Add cases for conditional-move and conditional-add operations [02/44] RISC-V/testsuite: Add cases for integer SFB cond-move operations [03/44] RISC-V: Reorder comment on SFB patterns [04/44] RISC-V: Sanitise NEED_EQ_NE_P case with `riscv_emit_int_compare' [05/44] RISC-V: Fix `mode' usage in `riscv_expand_conditional_move' [06/44] RISC-V: Avoid repeated GET_MODE calls in `riscv_expand_conditional_move' [07/44] RISC-V: Use `nullptr' in `riscv_expand_conditional_move' [08/44] RISC-V: Simplify EQ vs NE selection in `riscv_expand_conditional_move' [09/44] RISC-V: Rework branch costing model for if-conversion [10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations [11/44] RISC-V/testsuite: Add branchless cases for integer cond-move operations [12/44] RISC-V/testsuite: Add branched cases for FP cond-move operations [14/44] RISC-V: Also invert the cond-move condition for GEU and LEU [15/44] RISC-V/testsuite: Add branched cases for GEU and LEU cond-move operations [16/44] RISC-V/testsuite: Add branchless cases for GEU and LEU cond-move operations [17/44] RISC-V: Avoid extraneous EQ or NE operation in cond-move expansion [18/44] RISC-V/testsuite: Add branched cases for equality cond-move operations [19/44] RISC-V/testsuite: Add branchless cases for equality cond-move operations [20/44] RISC-V: Also accept constants for T-Head cond-move comparison operands [21/44] RISC-V: Also accept constants for T-Head cond-move data input operands [22/44] RISC-V: Fold all the cond-move variants together [23/44] RISC-V/testsuite: Add branched cases for T-Head non-equality cond moves [24/44] RISC-V/testsuite: Add branchless cases for T-Head non-equality cond moves [25/44] RISC-V: Implement `riscv_emit_unary' helper [26/44] RISC-V: Add `movMODEcc' implementation for generic targets [27/44] RISC-V/testsuite: Add branched cases for generic integer cond moves [28/44] RISC-V/testsuite: Add branchless cases for generic integer cond moves [29/44] RISC-V: Add `addMODEcc' implementation for generic targets [30/44] RISC-V/testsuite: Add branched cases for generic integer cond adds [31/44] RISC-V/testsuite: Add branchless cases for generic integer cond adds [32/44] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc' [33/44] RISC-V: Also allow FP conditions in `riscv_expand_conditional_move' [34/44] RISC-V: Provide FP conditional-branch instructions for if-conversion [35/44] RISC-V: Avoid extraneous integer comparison for FP comparisons [36/44] RISC-V/testsuite: Add branched cases for generic FP cond moves [37/44] RISC-V/testsuite: Add branchless cases for generic FP cond moves [38/44] RISC-V/testsuite: Add branched cases for generic FP cond adds [39/44] RISC-V/testsuite: Add branchless cases for generic FP cond adds [40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion [41/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations [42/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations [43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation [44/44] RISC-V/testsuite: Add branchless cases for FP NE cond-add operation

Index: gcc/gcc/testsuite/gcc.target/riscv/movdieq.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdieq.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=7 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + sub a5,a0,a1 + snez a5,a5 + neg a5,a5 + and a3,a5,a3 + not a5,a5 + and a5,a5,a2 + or a0,a3,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdige.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdige.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdige (int_t w, int_t x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + slt a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdigeu.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdigeu.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef unsigned int __attribute__ ((mode (DI))) int_t; + +int_t +movdigeu (int_t w, int_t x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + sltu a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdigt.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdigt.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdigt (int_t w, int_t x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + sgt a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdigtu.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdigtu.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef unsigned int __attribute__ ((mode (DI))) int_t; + +int_t +movdigtu (int_t w, int_t x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + sgtu a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdile.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdile.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdile (int_t w, int_t x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + sgt a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdileu.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdileu.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef unsigned int __attribute__ ((mode (DI))) int_t; + +int_t +movdileu (int_t w, int_t x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + sgtu a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdilt.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdilt.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdilt (int_t w, int_t x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + slt a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdiltu.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdiltu.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef unsigned int __attribute__ ((mode (DI))) int_t; + +int_t +movdiltu (int_t w, int_t x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + sltu a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdine.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdine.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + sub a5,a0,a1 + seqz a5,a5 + neg a5,a5 + and a3,a5,a3 + not a5,a5 + and a5,a5,a2 + or a0,a3,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsieq.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsieq.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=7 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=7 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + sub a5,a0,a1 + snez a5,a5 + neg a5,a5 + and a3,a5,a3 + not a5,a5 + and a5,a5,a2 + or a0,a3,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsige.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsige.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsige (int_t w, int_t x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + slt a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsigeu.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsigeu.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef unsigned int __attribute__ ((mode (SI))) int_t; + +int_t +movsigeu (int_t w, int_t x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + sltu a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsigt.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsigt.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsigt (int_t w, int_t x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + sgt a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsigtu.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsigtu.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef unsigned int __attribute__ ((mode (SI))) int_t; + +int_t +movsigtu (int_t w, int_t x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + sgtu a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsile.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsile.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsile (int_t w, int_t x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + sgt a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsileu.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsileu.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef unsigned int __attribute__ ((mode (SI))) int_t; + +int_t +movsileu (int_t w, int_t x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + sgtu a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsilt.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsilt.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsilt (int_t w, int_t x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + slt a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsiltu.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsiltu.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef unsigned int __attribute__ ((mode (SI))) int_t; + +int_t +movsiltu (int_t w, int_t x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + sltu a1,a0,a1 + neg a1,a1 + and a3,a1,a3 + not a1,a1 + and a1,a1,a2 + or a0,a3,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsine.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsine.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + sub a5,a0,a1 + seqz a5,a5 + neg a5,a5 + and a3,a5,a3 + not a5,a5 + and a5,a5,a2 + or a0,a3,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */

[28/44] RISC-V/testsuite: Add branchless cases for generic integer cond moves

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