| Message ID | c6b8c2739278b63e5e03c2a2095254fa0afedbda.1575914822.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V Hypervisor Extension v0.5 | expand |
On Mon, 09 Dec 2019 10:12:12 PST (-0800), Alistair Francis wrote: > Add a helper macro MSTATUS_MPV_ISSET() which will determine if the > MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu_bits.h | 11 +++++++++++ > target/riscv/cpu_helper.c | 4 ++-- > target/riscv/op_helper.c | 2 +- > target/riscv/translate.c | 2 +- > 4 files changed, 15 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 049032f2ae..dd012a514e 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -363,8 +363,19 @@ > #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ > #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ > #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ > +#if defined(TARGET_RISCV64) > #define MSTATUS_MTL 0x4000000000ULL > #define MSTATUS_MPV 0x8000000000ULL > +#elif defined(TARGET_RISCV32) > +#define MSTATUS_MTL 0x00000040 > +#define MSTATUS_MPV 0x00000080 > +#endif > + > +#ifdef TARGET_RISCV32 > +# define MSTATUS_MPV_ISSET(env) get_field(*env->mstatush, MSTATUS_MPV) > +#else > +# define MSTATUS_MPV_ISSET(env) get_field(*env->mstatus, MSTATUS_MPV) > +#endif > > #define MSTATUS64_UXL 0x0000000300000000ULL > #define MSTATUS64_SXL 0x0000000C00000000ULL > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index c2ad0bbce7..7166e6199e 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -314,7 +314,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > mode = get_field(*env->mstatus, MSTATUS_MPP); > > if (riscv_has_ext(env, RVH) && > - get_field(*env->mstatus, MSTATUS_MPV)) { > + MSTATUS_MPV_ISSET(env)) { > use_background = true; > } > } > @@ -714,7 +714,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > m_mode_two_stage = env->priv == PRV_M && > access_type != MMU_INST_FETCH && > get_field(*env->mstatus, MSTATUS_MPRV) && > - get_field(*env->mstatus, MSTATUS_MPV); > + MSTATUS_MPV_ISSET(env); > > hs_mode_two_stage = env->priv == PRV_S && > !riscv_cpu_virt_enabled(env) && > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index a0a631d722..b0b9890a15 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) > > target_ulong mstatus = *env->mstatus; > target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); > - target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV); > + target_ulong prev_virt = MSTATUS_MPV_ISSET(env); > mstatus = set_field(mstatus, > env->priv_ver >= PRIV_VERSION_1_10_0 ? > MSTATUS_MIE : MSTATUS_UIE << prev_priv, > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index dd93e12b45..0a28f208a2 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -752,7 +752,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->virt_enabled = riscv_cpu_virt_enabled(env); > if (env->priv_ver == PRV_M && > get_field(*env->mstatus, MSTATUS_MPRV) && > - get_field(*env->mstatus, MSTATUS_MPV)) { > + MSTATUS_MPV_ISSET(env)) { > ctx->virt_enabled = true; > } else if (env->priv == PRV_S && > !riscv_cpu_virt_enabled(env) && Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 049032f2ae..dd012a514e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -363,8 +363,19 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ +#if defined(TARGET_RISCV64) #define MSTATUS_MTL 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#elif defined(TARGET_RISCV32) +#define MSTATUS_MTL 0x00000040 +#define MSTATUS_MPV 0x00000080 +#endif + +#ifdef TARGET_RISCV32 +# define MSTATUS_MPV_ISSET(env) get_field(*env->mstatush, MSTATUS_MPV) +#else +# define MSTATUS_MPV_ISSET(env) get_field(*env->mstatus, MSTATUS_MPV) +#endif #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c2ad0bbce7..7166e6199e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -314,7 +314,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, mode = get_field(*env->mstatus, MSTATUS_MPP); if (riscv_has_ext(env, RVH) && - get_field(*env->mstatus, MSTATUS_MPV)) { + MSTATUS_MPV_ISSET(env)) { use_background = true; } } @@ -714,7 +714,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, m_mode_two_stage = env->priv == PRV_M && access_type != MMU_INST_FETCH && get_field(*env->mstatus, MSTATUS_MPRV) && - get_field(*env->mstatus, MSTATUS_MPV); + MSTATUS_MPV_ISSET(env); hs_mode_two_stage = env->priv == PRV_S && !riscv_cpu_virt_enabled(env) && diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index a0a631d722..b0b9890a15 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) target_ulong mstatus = *env->mstatus; target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); - target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV); + target_ulong prev_virt = MSTATUS_MPV_ISSET(env); mstatus = set_field(mstatus, env->priv_ver >= PRIV_VERSION_1_10_0 ? MSTATUS_MIE : MSTATUS_UIE << prev_priv, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index dd93e12b45..0a28f208a2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -752,7 +752,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->virt_enabled = riscv_cpu_virt_enabled(env); if (env->priv_ver == PRV_M && get_field(*env->mstatus, MSTATUS_MPRV) && - get_field(*env->mstatus, MSTATUS_MPV)) { + MSTATUS_MPV_ISSET(env)) { ctx->virt_enabled = true; } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu_bits.h | 11 +++++++++++ target/riscv/cpu_helper.c | 4 ++-- target/riscv/op_helper.c | 2 +- target/riscv/translate.c | 2 +- 4 files changed, 15 insertions(+), 4 deletions(-)