[v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1

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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI
	when V=1
Date: Mon,  9 Dec 2019 10:11:37 -0800
Message-Id: <b1b5cc3f1f924b8dadb615feac199df7ab266335.1575914822.git.alistair.francis@wdc.com>
In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com>
References: <cover.1575914822.git.alistair.francis@wdc.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: list
Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Message ID	b1b5cc3f1f924b8dadb615feac199df7ab266335.1575914822.git.alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: U6OAfgGlMhagaUT1KWsP86v2txHAYTs83vy+5IDmxNcJ/KKIc1axkylpoYpf5M4Vqiho+RdSLP qwmgRJEcabBBfzJNY+g92I7orczm5kOQb6rQ5JXukONZmQtjDSUwYLgb7daGiOqgSqhBXIpWIF 2eo1UQGI5vRSDsr7QHynHJK9wZL91Fcq4L324x2IW3FKRbRN16XmrcnM76bR3ao/918ekthD4T cm3fzie/aoizzUpSaOkRVNGvZEAwZp/3XaVpfGasNeVvy13pvv6dwCleVW41fPpfCRhtrocV3X dFw= IronPort-SDR: f+dCn0Xe3dPlCDA3C1gYB6Io20BFFVOJAoubgxrShWHkrWJeCb8Ub+3DEgGNsV3j5ym1Pn7cBt Ke2rBUs1Yvuo5sY31Ek9ml0Fyk5/BypVCFXZ0er8FwQjbQdCtqlFco6ar74ifFvLuumabrR0Lq VNpxfEZHSdCwX45waglqnrsrTTbFvw0O3jzKQGtsB6/sPkxMKKkfhkU4SkQZUA7Qj6MLf28SPY 0U7/d/VWyVEUIh5jg114wIENxHHmUVRbBI/phfMsIg7UkPdZLHnDQ3NcNlNssAm1J0sEbDO+cC zzUzp5uUfQl9vgfLYrpqYxNQ IronPort-SDR: Nx/ONmtuUC5/tRqFPD2IDWEn4zy1z83RMi+PQEXMjLfcSqYbjcRy0oQc0dP+F/9QM7UXXIZ8lT zUh6yruwBdAfsg1xG/XFvdPEADIhVzR/bNFTYA/OG+NspV9erXuS8CMNWIYd80ip6XHv+evOz4 6AGS3WklFF81fcubxIvDlwCjBl0AIInHt2M59cQUov42e/4SRvy3ixF9fRIsYSyKpbHcswNJNI L8k8htQ8Naj7f9wXfOjsCmZrXn6XA8rpEmjqwJJNidncLMGdcOQw2prm3wr5GbXTprr5e1hRyq ZZw= WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1 Date: Mon, 9 Dec 2019 10:11:37 -0800 Message-Id: <b1b5cc3f1f924b8dadb615feac199df7ab266335.1575914822.git.alistair.francis@wdc.com> In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com> References: <cover.1575914822.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Add RISC-V Hypervisor Extension v0.5 \| expand [v1,00/36] Add RISC-V Hypervisor Extension v0.5 [v1,01/36] target/riscv: Convert MIP CSR to target_ulong [v1,02/36] target/riscv: Don't set write permissions on dirty PTEs [v1,03/36] target/riscv: Add the Hypervisor extension [v1,04/36] target/riscv: Add the Hypervisor CSRs to CPUState [v1,05/36] target/riscv: Add support for the new execption numbers [v1,06/36] target/riscv: Rename the H irqs to VS irqs [v1,07/36] target/riscv: Add the virtulisation mode [v1,08/36] target/riscv: Add the force HS exception mode [v1,09/36] target/riscv: Fix CSR perm checking for HS mode [v1,10/36] target/riscv: Print priv and virt in disas log [v1,11/36] target/riscv: Dump Hypervisor registers if enabled [v1,12/36] target/riscv: Add Hypervisor CSR access functions [v1,13/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,14/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,15/36] target/riscv: Convert mstatus to pointers [v1,16/36] target/riscv: Add virtual register swapping function [v1,17/36] target/riscv: Set VS bits in mideleg for Hyp extension [v1,18/36] target/riscv: Extend the MIE CSR to support virtulisation [v1,19/36] target/riscv: Extend the SIP CSR to support virtulisation [v1,20/36] target/riscv: Add support for virtual interrupt setting [v1,21/36] target/ricsv: Flush the TLB on virtulisation mode changes [v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1 [v1,23/36] target/riscv: Add hypvervisor trap support [v1,24/36] target/riscv: Add Hypervisor trap return support [v1,25/36] target/riscv: Add hfence instructions [v1,26/36] target/riscv: Remove the hret instruction [v1,27/36] target/riscv: Disable guest FP support based on virtual status [v1,28/36] target/riscv: Mark both sstatus and vsstatus as dirty [v1,29/36] target/riscv: Respect MPRV and SPRV for floating point ops [v1,30/36] target/riscv: Allow specifying MMU stage [v1,31/36] target/riscv: Implement second stage MMU [v1,32/36] target/riscv: Raise the new execptions when 2nd stage translation fails [v1,33/36] target/riscv: Set htval and mtval2 on execptions [v1,34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR [v1,35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [v1,36/36] target/riscv: Allow enabling the Hypervisor extension

[v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1

Commit Message

Patch