Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   330 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[for,4.1,v1,6/6] riscv: Add a generic spike machine RISC-V: Allow specifying CPU ISA via command line - - - - 0 0 0 2019-03-19 Alistair Francis New
[for,4.1,v1,5/6] target/riscv: Remove the generic no MMU CPUs RISC-V: Allow specifying CPU ISA via command line - - - - 0 0 0 2019-03-19 Alistair Francis New
[for,4.1,v1,4/6] target/riscvL Remove the unused any CPU RISC-V: Allow specifying CPU ISA via command line - - - - 0 0 0 2019-03-19 Alistair Francis New
[for,4.1,v1,3/6] riscv: virt: Allow specifying a CPU via commandline RISC-V: Allow specifying CPU ISA via command line - - - - 0 0 0 2019-03-19 Alistair Francis New
[for,4.1,v1,2/6] target/riscv: Create settable CPU properties RISC-V: Allow specifying CPU ISA via command line - - - - 0 0 0 2019-03-19 Alistair Francis New
[for,4.1,v1,1/6] target/riscv: Fall back to generating a RISC-V CPU RISC-V: Allow specifying CPU ISA via command line - - - - 0 0 0 2019-03-19 Alistair Francis New
[v1,12/12] target/riscv: Remove unused struct Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,11/12] riscv: sifive_u: Allow up to 4 CPUs to be created Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,10/12] RISC-V: Update load reservation comment in do_interrupt Untitled series #97460 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,09/12] RISC-V: Convert trap debugging to trace events Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,08/12] RISC-V: Add support for vectored interrupts Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,07/12] RISC-V: Change local interrupts from edge to level Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,06/12] RISC-V: linux-user support for RVE ABI Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,05/12] elf: Add RISC-V PSABI ELF header defines Upstream RISC-V fork patches, part 4 - - 1 - 0 0 0 2019-03-16 Alistair Francis New
[v1,04/12] RISC-V: Remove unnecessary disassembler constraints Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,03/12] RISC-V: Allow interrupt controllers to claim interrupts Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,01/12] riscv: pmp: Log pmp access errors as guest errors Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-03-16 Alistair Francis New
[v1,1/1] riscv: plic: Set msi_nonbroken as true [v1,1/1] riscv: plic: Set msi_nonbroken as true - - - 1 0 0 0 2019-03-15 Alistair Francis New
[v2,11/11] riscv: sifive_u: Allow up to 4 CPUs to be created Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,10/11] RISC-V: Update load reservation comment in do_interrupt Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,09/11] RISC-V: Convert trap debugging to trace events Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,08/11] RISC-V: Add support for vectored interrupts Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,07/11] RISC-V: Change local interrupts from edge to level Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,06/11] RISC-V: linux-user support for RVE ABI Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,05/11] elf: Add RISC-V PSABI ELF header defines Upstream RISC-V fork patches, part 4 - - 1 - 0 0 0 2019-02-21 Alistair Francis New
[v2,04/11] RISC-V: Remove unnecessary disassembler constraints Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,03/11] RISC-V: Allow interrupt controllers to claim interrupts Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,02/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v2,01/11] riscv: pmp: Log pmp access errors as guest errors Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-21 Alistair Francis New
[v1,11/11] RISC-V: Update load reservation comment in do_interrupt Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,10/11] RISC-V: Convert trap debugging to trace events Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,09/11] RISC-V: Add support for vectored interrupts Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,08/11] RISC-V: Change local interrupts from edge to level Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,07/11] RISC-V: linux-user support for RVE ABI Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,06/11] elf: Add RISC-V PSABI ELF header defines Upstream RISC-V fork patches, part 4 - - 1 - 0 0 0 2019-02-09 Alistair Francis New
[v1,05/11] RISC-V: Remove unnecessary disassembler constraints Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,04/11] RISC-V: Allow interrupt controllers to claim interrupts Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,03/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,02/11] riscv: pmp: Log pmp access errors as guest errors Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v1,01/11] riscv: Ensure the kernel start address is correctly cast Upstream RISC-V fork patches, part 4 - - - - 0 0 0 2019-02-09 Alistair Francis New
[v3,1/1] riscv: Ensure the kernel start address is correctly cast [v3,1/1] riscv: Ensure the kernel start address is correctly cast - - 1 - 0 0 0 2019-01-24 Alistair Francis New
[v1,8/8] RISC-V: Add misa runtime write support Upstream RISC-V fork patches, part 3 - - 1 - 0 0 0 2019-01-14 Alistair Francis New
[v1,7/8] RISC-V: Add misa.MAFD checks to translate Upstream RISC-V fork patches, part 3 - - 1 - 0 0 0 2019-01-14 Alistair Francis New
[v1,6/8] RISC-V: Add misa to DisasContext Upstream RISC-V fork patches, part 3 - - 1 - 0 0 0 2019-01-14 Alistair Francis New
[v1,5/8] RISC-V: Add priv_ver to DisasContext Upstream RISC-V fork patches, part 3 - - 1 - 0 0 0 2019-01-14 Alistair Francis New
[v1,4/8] RISC-V: Use riscv prefix consistently on cpu helpers Upstream RISC-V fork patches, part 3 - - 1 - 0 0 0 2019-01-14 Alistair Francis New
[v1,3/8] RISC-V: Implement mstatus.TSR/TW/TVM Upstream RISC-V fork patches, part 3 - - - - 0 0 0 2019-01-14 Alistair Francis New
[v1,2/8] RISC-V: Mark mstatus.fs dirty Upstream RISC-V fork patches, part 3 - - 1 - 0 0 0 2019-01-14 Alistair Francis New
[v1,1/8] RISC-V: Split out mstatus_fs from tb_flags Upstream RISC-V fork patches, part 3 - - 1 - 0 0 0 2019-01-14 Alistair Francis New
[v2,1/1] riscv: Ensure the kernel start address is correctly cast [v2,1/1] riscv: Ensure the kernel start address is correctly cast - - - - 0 0 0 2019-01-12 Alistair Francis New
[v1,1/1] default-configs: Enable USB support for RISC-V machines [v1,1/1] default-configs: Enable USB support for RISC-V machines - - 1 - 0 0 0 2019-01-10 Alistair Francis New
[v1,3/3] RISC-V: Implement existential predicates for CSRs Upstream more RISC-V fork patches - - - - 0 0 0 2019-01-04 Alistair Francis New
[v1,2/3] RISC-V: Implement atomic mip/sip CSR updates Upstream more RISC-V fork patches - - - - 0 0 0 2019-01-04 Alistair Francis New
[v1,1/3] RISC-V: Implement modular CSR helper interface Upstream more RISC-V fork patches - - - - 0 0 0 2019-01-04 Alistair Francis New
[v2,23/23] configure: Add support for building RISC-V host Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,22/23] dias: Add RISC-V support Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,21/23] tcg: Add RISC-V cpu signal handler Add RISC-V TCG backend support - - - - 0 0 0 2018-12-19 Alistair Francis New
[v2,20/23] riscv: tcg-target: Add the target init code Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,19/23] riscv: tcg-target: Add the prologue generation and register the JIT Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,18/23] riscv: tcg-target: Add the out op decoder Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,17/23] riscv: tcg-target: Add direct load and store instructions Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,16/23] riscv: tcg-target: Add slowpath load and store instructions Add RISC-V TCG backend support - - - - 0 0 0 2018-12-19 Alistair Francis New
[v2,15/23] riscv: tcg-target: Add branch and jump instructions Add RISC-V TCG backend support - - - - 0 0 0 2018-12-19 Alistair Francis New
[v2,14/23] riscv: tcg-target: Add the add2 and sub2 instructions Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,13/23] riscv: tcg-target: Add the out load and store instructions Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,12/23] riscv: tcg-target: Add the extract instructions Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,11/23] riscv: tcg-target: Add the mov and movi instruction Add RISC-V TCG backend support - - - - 0 0 0 2018-12-19 Alistair Francis New
[v2,10/23] riscv: tcg-target: Add the relocation functions Add RISC-V TCG backend support - - - - 0 0 0 2018-12-19 Alistair Francis New
[v2,09/23] riscv: tcg-target: Add the instruction emitters Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,08/23] riscv: tcg-target: Add the immediate encoders Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,07/23] riscv: tcg-target: Add support for the constraints Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,06/23] riscv: Add the tcg target registers Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,05/23] riscv: Add the tcg-target header file Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,04/23] exec: Add RISC-V GCC poison macro Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,03/23] linux-user: Add host dependency for RISC-V 64-bit Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,02/23] linux-user: Add host dependency for RISC-V 32-bit Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v2,01/23] elf.h: Add the RISCV ELF magic numbers Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-19 Alistair Francis New
[v1,1/1] target/riscv/pmp.c: Fix pmp_decode_napot() [v1,1/1] target/riscv/pmp.c: Fix pmp_decode_napot() - - - - 0 0 0 2018-12-14 Alistair Francis New
[v1,5/5] sifive_uart: Implement interrupt pending register Misc RISC-V fixes - - 2 - 0 0 0 2018-12-14 Alistair Francis New
[v1,4/5] RISC-V: Enable second UART on sifive_e and sifive_u Misc RISC-V fixes - - 1 - 0 0 0 2018-12-14 Alistair Francis New
[v1,3/5] RISC-V: Fix PLIC pending bitfield reads Misc RISC-V fixes - - 1 - 0 0 0 2018-12-14 Alistair Francis New
[v1,2/5] RISC-V: Fix CLINT timecmp low 32-bit writes Misc RISC-V fixes - - 1 - 0 0 0 2018-12-14 Alistair Francis New
[v1,1/5] RISC-V: Add hartid and \n to interrupt logging Misc RISC-V fixes - - 1 - 0 0 0 2018-12-14 Alistair Francis New
[v1,1/1] sifive_u: Set 'clock-frequency' DT property for SiFive UART [v1,1/1] sifive_u: Set 'clock-frequency' DT property for SiFive UART - - - - 0 0 0 2018-12-13 Alistair Francis New
[v1,1/1] sifive_u: Add clock DT node for GEM ethernet [v1,1/1] sifive_u: Add clock DT node for GEM ethernet - - - - 0 0 0 2018-12-13 Alistair Francis New
[v1,1/1] tcg: mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS [v1,1/1] tcg: mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,23/23] configure: Add support for building RISC-V host Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,22/23] dias: Add RISC-V support Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,21/23] tcg: Add RISC-V cpu signal handler Add RISC-V TCG backend support - - - - 0 0 0 2018-12-12 Alistair Francis New
[v1,20/23] riscv: tcg-target: Add the target init code Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,19/23] riscv: tcg-target: Add the prologue generation and register the JIT Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,18/23] riscv: tcg-target: Add the out op decoder Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,17/23] riscv: tcg-target: Add direct load and store instructions Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,16/23] riscv: tcg-target: Add slowpath load and store instructions Add RISC-V TCG backend support - - - - 0 0 0 2018-12-12 Alistair Francis New
[v1,15/23] riscv: tcg-target: Add branch and jump instructions Add RISC-V TCG backend support - - - - 0 0 0 2018-12-12 Alistair Francis New
[v1,14/23] riscv: tcg-target: Add the add2 and sub2 instructions Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,13/23] riscv: tcg-target: Add the out load and store instructions Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,12/23] riscv: tcg-target: Add the extract instructions Add RISC-V TCG backend support - - 1 - 0 0 0 2018-12-12 Alistair Francis New
[v1,11/23] riscv: tcg-target: Add the mov and movi instruction Add RISC-V TCG backend support - - - - 0 0 0 2018-12-12 Alistair Francis New
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