Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   552 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v3,7/7] riscv/virt: Jump to pflash if specified [v3,1/7] riscv/sifive_u: Add L2-LIM cache memory - - 2 1 0 0 0 2019-10-08 Alistair Francis New
[v3,6/7] riscv/virt: Add the PFlash CFI01 device [v3,1/7] riscv/sifive_u: Add L2-LIM cache memory - - 1 1 0 0 0 2019-10-08 Alistair Francis New
[v3,5/7] riscv/virt: Manually define the machine [v3,1/7] riscv/sifive_u: Add L2-LIM cache memory - - 1 1 0 0 0 2019-10-08 Alistair Francis New
[v3,4/7] riscv/sifive_u: Add the start-in-flash property [v3,1/7] riscv/sifive_u: Add L2-LIM cache memory - - 1 1 0 0 0 2019-10-08 Alistair Francis New
[v3,3/7] riscv/sifive_u: Manually define the machine [v3,1/7] riscv/sifive_u: Add L2-LIM cache memory - - 1 1 0 0 0 2019-10-08 Alistair Francis New
[v3,2/7] riscv/sifive_u: Add QSPI memory region [v3,1/7] riscv/sifive_u: Add L2-LIM cache memory - - 1 - 0 0 0 2019-10-08 Alistair Francis New
[v3,1/7] riscv/sifive_u: Add L2-LIM cache memory [v3,1/7] riscv/sifive_u: Add L2-LIM cache memory - - 1 - 0 0 0 2019-10-08 Alistair Francis New
[v1,1/1] target/riscv: Remove atomic accesses to MIP CSR [v1,1/1] target/riscv: Remove atomic accesses to MIP CSR - - 1 - 0 0 0 2019-10-08 Alistair Francis New
[v2,2/2] RISC-V: Implement cpu_do_transaction_failed RISC-V: Convert to do_transaction_failed hook - - 2 - 0 0 0 2019-10-08 Alistair Francis New
[v2,1/2] RISC-V: Handle bus errors in the page table walker RISC-V: Convert to do_transaction_failed hook - - 2 - 0 0 0 2019-10-08 Alistair Francis New
[v2,1/1] riscv/boot: Fix possible memory leak [v2,1/1] riscv/boot: Fix possible memory leak - - 3 - 0 0 0 2019-10-03 Alistair Francis New
[v1,1/1] riscv/boot: Fix possible memory leak [v1,1/1] riscv/boot: Fix possible memory leak - - 3 - 0 0 0 2019-10-02 Alistair Francis New
[v1,1/1] target/riscv: Print CPU and privledge in disas [v1,1/1] target/riscv: Print CPU and privledge in disas - - 2 1 0 0 0 2019-09-27 Alistair Francis New
[v2,7/7] riscv/virt: Jump to pflash if specified RISC-V: Add more machine memory - - 2 1 0 0 0 2019-09-27 Alistair Francis New
[v2,6/7] riscv/virt: Add the PFlash CFI01 device RISC-V: Add more machine memory - - 1 1 0 0 0 2019-09-27 Alistair Francis New
[v2,5/7] riscv/virt: Manually define the machine RISC-V: Add more machine memory - - 1 1 0 0 0 2019-09-27 Alistair Francis New
[v2,4/7] riscv/sifive_u: Add the start-in-flash property RISC-V: Add more machine memory - - 1 - 0 0 0 2019-09-27 Alistair Francis New
[v2,3/7] riscv/sifive_u: Manually define the machine RISC-V: Add more machine memory - - 1 1 0 0 0 2019-09-27 Alistair Francis New
[v2,2/7] riscv/sifive_u: Add QSPI memory region RISC-V: Add more machine memory - - 1 - 0 0 0 2019-09-27 Alistair Francis New
[v2,1/7] riscv/sifive_u: Add L2-LIM cache memory RISC-V: Add more machine memory - - 1 - 0 0 0 2019-09-27 Alistair Francis New
[v1,6/6] riscv/virt: Jump to pflash if specified RISC-V: Add more machine memory - - 2 - 0 0 0 2019-09-19 Alistair Francis New
[v1,5/6] riscv/virt: Add the PFlash CFI01 device RISC-V: Add more machine memory - - - - 0 0 0 2019-09-19 Alistair Francis New
[v1,4/6] riscv/sifive_u: Add the start-in-flash property RISC-V: Add more machine memory - - - - 0 0 0 2019-09-19 Alistair Francis New
[v1,3/6] riscv/sifive_u: Manually define the machine RISC-V: Add more machine memory - - - - 0 0 0 2019-09-19 Alistair Francis New
[v1,2/6] riscv/sifive_u: Add QSPI memory region RISC-V: Add more machine memory - - - - 0 0 0 2019-09-19 Alistair Francis New
[v1,1/6] riscv/sifive_u: Add L2-LIM cache memory RISC-V: Add more machine memory - - - - 0 0 0 2019-09-19 Alistair Francis New
[v1,2/2] RISC-V: Implement cpu_do_transaction_failed RISC-V: Convert to do_transaction_failed hook - - 1 - 0 0 0 2019-09-17 Alistair Francis New
[v1,1/2] RISC-V: Handle bus errors in the page table walker RISC-V: Convert to do_transaction_failed hook - - 1 - 0 0 0 2019-09-17 Alistair Francis New
[v1,28/28] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,25/28] target/riscv: Call the second stage MMU in virtualisation mode Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,24/28] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,23/28] target/riscv: Allow specifying number of MMU stages Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,22/28] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,21/28] target/riscv: Respect MPRV and SPRV for floating point ops Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,20/28] target/riscv: Mark both sstatus and vsstatus as dirty Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,19/28] target/riscv: Disable guest FP support based on virtual status Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,18/28] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,17/28] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,16/28] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,15/28] riscv: plic: Always set sip.SEIP bit for HS Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,14/28] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,13/28] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,12/28] target/riscv: Add support for virtual interrupt setting Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,11/28] target/riscv: Add background register swapping function Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,10/28] target/riscv: Convert mie and mstatus to pointers Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,09/28] target/riscv: Add Hypervisor virtual CSRs accesses Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,08/28] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,07/28] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,06/28] target/riscv: Print priv and virt in disas log Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,05/28] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension v0.4 - - 2 - 0 0 0 2019-08-23 Alistair Francis New
[v1,04/28] target/riscv: Fix CSR perm checking for HS mode Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,03/28] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,02/28] target/riscv: Add the virtulisation mode Untitled series #127095 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,01/28] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v4,7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point RISC-V: Hypervisor prep work part 2 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v4,6/7] target/riscv: Fix mstatus dirty mask RISC-V: Hypervisor prep work part 2 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v4,5/7] target/riscv: Use both register name and ABI name RISC-V: Hypervisor prep work part 2 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v4,4/7] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - - 2 - 0 0 0 2019-08-23 Alistair Francis New
[v4,3/7] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - - 4 - 0 0 0 2019-08-23 Alistair Francis New
[v4,2/7] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - - 4 - 0 0 0 2019-08-23 Alistair Francis New
[v4,1/7] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v3,7/7] target/riscv: Convert mip to target_ulong RISC-V: Hypervisor prep work part 2 - - 1 - 0 0 0 2019-08-15 Alistair Francis New
[v3,6/7] target/riscv: Fix mstatus dirty mask RISC-V: Hypervisor prep work part 2 - - 1 - 0 0 0 2019-08-15 Alistair Francis New
[v3,5/7] target/riscv: Use both register name and ABI name RISC-V: Hypervisor prep work part 2 - - 1 - 0 0 0 2019-08-15 Alistair Francis New
[v3,4/7] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - - 2 - 0 0 0 2019-08-15 Alistair Francis New
[v3,3/7] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - - 4 - 0 0 0 2019-08-15 Alistair Francis New
[v3,2/7] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - - 4 - 0 0 0 2019-08-15 Alistair Francis New
[v3,1/7] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - - 1 - 0 0 0 2019-08-15 Alistair Francis New
[PATCH-4.2,v2,5/5] target/riscv: Fix Floating Point register names RISC-V: Hypervisor prep work part 2 - - - - 0 0 0 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,4/5] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - - - - 0 0 0 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,3/5] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - - 2 - 0 0 0 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,2/5] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - - 3 - 0 0 0 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,1/5] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - - - - 0 0 0 2019-07-30 Alistair Francis New
[PATCH-4.2,v1,6/6] target/riscv: Fix Floating Point register names RISC-V: Hypervisor prep work part 2 - - - - 0 0 0 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,5/6] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - - - - 0 0 0 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,4/6] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - - 2 - 0 0 0 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,3/6] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - - 3 - 0 0 0 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,2/6] target/riscv: Remove strict perm checking for CSR R/W RISC-V: Hypervisor prep work part 2 - - - - 0 0 0 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,1/6] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - - - - 0 0 0 2019-07-25 Alistair Francis New
[v2,1/1] riscv/boot: Fixup the RISC-V firmware warning [v2,1/1] riscv/boot: Fixup the RISC-V firmware warning - - 1 - 0 0 0 2019-07-22 Alistair Francis New
[v1,1/1] riscv/boot: Fixup the RISC-V firmware warning [v1,1/1] riscv/boot: Fixup the RISC-V firmware warning - - 1 - 0 0 0 2019-07-19 Alistair Francis New
[v3,2/2] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add default OpenSBI ROM - - 2 2 0 0 0 2019-07-16 Alistair Francis New
[v3,1/2] roms: Add OpenSBI version 0.4 RISC-V: Add default OpenSBI ROM - - 2 1 0 0 0 2019-07-16 Alistair Francis New
[v2,2/2] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add default OpenSBI ROM - - 2 2 0 0 0 2019-07-11 Alistair Francis New
[v2,1/2] roms: Add OpenSBI version 0.4 RISC-V: Add default OpenSBI ROM - - 2 1 0 0 0 2019-07-11 Alistair Francis New
[v1,2/2] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add default OpenSBI ROM - - 1 1 0 0 0 2019-07-08 Alistair Francis New
[v1,1/2] roms: Add OpenSBI version 0.4 RISC-V: Add default OpenSBI ROM - - 1 - 0 0 0 2019-07-08 Alistair Francis New
fixup! roms: Add OpenSBI version 0.3 fixup! roms: Add OpenSBI version 0.3 - - - - 0 0 0 2019-06-28 Alistair Francis New
[v1,1/1] hw/scsi: Report errors and sense to guests through scsi-block [v1,1/1] hw/scsi: Report errors and sense to guests through scsi-block - - - - 0 0 0 2019-06-26 Alistair Francis New
[v2,4/4] target/riscv: Implement riscv_cpu_unassigned_access Miscellaneous patches from the RISC-V fork - - - - 0 0 0 2019-06-24 Alistair Francis New
[v2,3/4] disas/riscv: Fix `rdinstreth` constraint Miscellaneous patches from the RISC-V fork - - - - 0 0 0 2019-06-24 Alistair Francis New
[v2,2/4] disas/riscv: Disassemble reserved compressed encodings as illegal Miscellaneous patches from the RISC-V fork - - - - 0 0 0 2019-06-24 Alistair Francis New
[v2,1/4] target/riscv: Fix PMP range boundary address bug Miscellaneous patches from the RISC-V fork - - 2 - 0 0 0 2019-06-24 Alistair Francis New
[v1,5/5] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add firmware loading support and default - - 1 1 0 0 0 2019-06-24 Alistair Francis New
[v1,4/5] roms: Add OpenSBI version 0.3 RISC-V: Add firmware loading support and default - - 1 1 0 0 0 2019-06-24 Alistair Francis New
[v1,3/5] hw/riscv: Extend the kernel loading support RISC-V: Add firmware loading support and default - - 1 1 0 0 0 2019-06-24 Alistair Francis New
[v1,2/5] hw/riscv: Add support for loading a firmware RISC-V: Add firmware loading support and default - - 1 1 0 0 0 2019-06-24 Alistair Francis New
[v1,1/5] hw/riscv: Split out the boot functions RISC-V: Add firmware loading support and default - - 1 1 0 0 0 2019-06-24 Alistair Francis New
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