Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1748 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,v2,12/12] hw/riscv/boot: Check the error of fdt_pack() [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,11/12] hw/riscv: opentitan: Add the flash alias [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,10/12] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,09/12] char: ibex_uart: Update the register layout [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,07/12] hw/riscv: sifive_u: Correct the CLINT timebase frequency [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,06/12] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,05/12] target/riscv: hardwire bits in hideleg and hedeleg [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 2 - --- 2021-07-15 Alistair Francis New
[PULL,v2,04/12] docs/system: riscv: Add documentation for virt machine [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,02/12] target/riscv: csr: Remove redundant check in fp csr read/write routines [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,01/12] target/riscv: pmp: Fix some typos [PULL,v2,01/12] target/riscv: pmp: Fix some typos - - 2 - --- 2021-07-15 Alistair Francis New
[PULL,v2,00/12] riscv-to-apply queue - - - - --- 2021-07-15 Alistair Francis New
[v2,1/1] hw/riscv/boot: Check the error of fdt_pack() [v2,1/1] hw/riscv/boot: Check the error of fdt_pack() - 1 1 - --- 2021-07-14 Alistair Francis New
[v2,5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 - --- 2021-07-14 Alistair Francis New
[v2,4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 3 1 --- 2021-07-14 Alistair Francis New
[v2,3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 - --- 2021-07-14 Alistair Francis New
[v2,2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 1 --- 2021-07-14 Alistair Francis New
[v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 3 1 --- 2021-07-14 Alistair Francis New
[v1,1/1] hw/riscv/boot: Check the error of fdt_pack() [v1,1/1] hw/riscv/boot: Check the error of fdt_pack() - 1 1 - --- 2021-07-14 Alistair Francis New
[PULL,11/11] hw/riscv: opentitan: Add the flash alias [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,09/11] char: ibex_uart: Update the register layout [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,05/11] target/riscv: hardwire bits in hideleg and hedeleg [PULL,01/11] target/riscv: pmp: Fix some typos - - 2 - --- 2021-07-12 Alistair Francis New
[PULL,04/11] docs/system: riscv: Add documentation for virt machine [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,01/11] target/riscv: pmp: Fix some typos [PULL,01/11] target/riscv: pmp: Fix some typos - - 2 - --- 2021-07-12 Alistair Francis New
[PULL,00/11] riscv-to-apply queue - - - - --- 2021-07-12 Alistair Francis New
[v2,3/3] hw/riscv: opentitan: Add the flash alias Updates to the OpenTitan machine - - 1 - --- 2021-07-09 Alistair Francis New
[v2,2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Updates to the OpenTitan machine - - 1 - --- 2021-07-09 Alistair Francis New
[v2,1/3] char: ibex_uart: Update the register layout Updates to the OpenTitan machine - - 1 - --- 2021-07-09 Alistair Francis New
[v1,5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 - --- 2021-07-09 Alistair Francis New
[v1,4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 - --- 2021-07-09 Alistair Francis New
[v1,3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 - --- 2021-07-09 Alistair Francis New
[v1,2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - - - --- 2021-07-09 Alistair Francis New
[v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 3 - --- 2021-07-09 Alistair Francis New
[v1,3/3] hw/riscv: opentitan: Add the flash alias Updates to the OpenTitan machine - - - - --- 2021-07-02 Alistair Francis New
[v1,2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Updates to the OpenTitan machine - - 1 - --- 2021-07-02 Alistair Francis New
[v1,1/3] char: ibex_uart: Update the register layout Updates to the OpenTitan machine - - 1 - --- 2021-07-02 Alistair Francis New
[PULL,7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - - 1 - --- 2021-06-24 Alistair Francis New
[PULL,6/7] hw/timer: Initial commit of Ibex Timer [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - - 1 - --- 2021-06-24 Alistair Francis New
[PULL,5/7] hw/char/ibex_uart: Make the register layout private [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - - 1 - --- 2021-06-24 Alistair Francis New
[PULL,4/7] hw/char: QOMify sifive_uart [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - - 2 - --- 2021-06-24 Alistair Francis New
[PULL,3/7] hw/char: Consistent function names for sifive_uart [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - - 2 - --- 2021-06-24 Alistair Francis New
[PULL,2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 1 1 1 --- 2021-06-24 Alistair Francis New
[PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 1 1 - --- 2021-06-24 Alistair Francis New
[PULL,0/7] riscv-to-apply queue - - - - --- 2021-06-24 Alistair Francis New
[v3,3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer OpenTitan: Add support for the RISC-V timer - - 1 - --- 2021-06-18 Alistair Francis New
[v3,2/3] hw/timer: Initial commit of Ibex Timer OpenTitan: Add support for the RISC-V timer - - 1 - --- 2021-06-18 Alistair Francis New
[v3,1/3] hw/char/ibex_uart: Make the register layout private OpenTitan: Add support for the RISC-V timer - - 1 - --- 2021-06-18 Alistair Francis New
[v2,3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer hw/riscv: OpenTitan: Add support for the RISC-V timer - - 1 - --- 2021-06-08 Alistair Francis New
[v2,2/3] hw/timer: Initial commit of Ibex Timer hw/riscv: OpenTitan: Add support for the RISC-V timer - - - - --- 2021-06-08 Alistair Francis New
[v2,1/3] hw/char/ibex_uart: Make the register layout private hw/riscv: OpenTitan: Add support for the RISC-V timer - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,32/32] target/riscv: rvb: add b-ext version cpu option [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,31/32] target/riscv: rvb: support and turn on B-extension from command line [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,30/32] target/riscv: rvb: add/shift with prefix zero-extend [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,29/32] target/riscv: rvb: address calculation [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,28/32] target/riscv: rvb: generalized or-combine [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,27/32] target/riscv: rvb: generalized reverse [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,26/32] target/riscv: rvb: rotate (left/right) [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,25/32] target/riscv: rvb: shift ones [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,24/32] target/riscv: rvb: single-bit instructions [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,22/32] target/riscv: rvb: sign-extend instructions [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,21/32] target/riscv: rvb: min/max instructions [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,20/32] target/riscv: rvb: pack two words into one register [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,19/32] target/riscv: rvb: logic-with-negate [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,18/32] target/riscv: rvb: count bits set [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,17/32] target/riscv: rvb: count leading/trailing zeros [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,16/32] target/riscv: reformat @sh format encoding for B-extension [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,15/32] target/riscv: Pass the same value to oprsz and maxsz. [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,14/32] target/riscv/pmp: Add assert for ePMP operations [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 2 - --- 2021-06-08 Alistair Francis New
[PULL,13/32] target/riscv: Dump CSR mscratch/sscratch/satp [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,11/32] target/riscv: Do not include 'pmp.h' in user emulation [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 2 - --- 2021-06-08 Alistair Francis New
[PULL,10/32] docs/system: Move the RISC-V -bios information to removed [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,09/32] target/riscv: fix wfi exception behavior [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,07/32] hw/riscv: Use macros for BIOS image names [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,06/32] docs/system/riscv: sifive_u: Document '-dtb' usage [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,05/32] docs/system/riscv: Correct the indentation level of supported devices [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,04/32] hw/riscv: Support the official PLIC DT bindings [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,03/32] hw/riscv: Support the official CLINT DT bindings [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,00/32] riscv-to-apply queue - - - - --- 2021-06-08 Alistair Francis New
[v1,3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer hw/riscv: OpenTitan: Add support for the RISC-V timer - - - - --- 2021-05-31 Alistair Francis New
[v1,2/3] hw/timer: Initial commit of Ibex Timer hw/riscv: OpenTitan: Add support for the RISC-V timer - - - - --- 2021-05-31 Alistair Francis New
[v1,1/3] hw/char/ibex_uart: Make the register layout private hw/riscv: OpenTitan: Add support for the RISC-V timer - - 1 - --- 2021-05-31 Alistair Francis New
[v1,1/1] target/riscv: Use target_ulong for the DisasContext misa [v1,1/1] target/riscv: Use target_ulong for the DisasContext misa - 1 1 - --- 2021-05-31 Alistair Francis New
[v1,1/1] target/riscv/pmp: Add assert for ePMP operations [v1,1/1] target/riscv/pmp: Add assert for ePMP operations - 1 2 - --- 2021-05-20 Alistair Francis New
[PULL,v3,42/42] target/riscv: Fix the RV64H decode comment [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,41/42] target/riscv: Consolidate RV32/64 16-bit instructions [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,40/42] target/riscv: Consolidate RV32/64 32-bit instructions [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,39/42] target/riscv: Remove an unused CASE_OP_32_64 macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,38/42] target/riscv: Remove the unused HSTATUS_WPRI macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-11 Alistair Francis New
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