| Message ID | d43f1c34d02514d3df0527c20718725a36684887.1575914822.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V Hypervisor Extension v0.5 | expand |
On Mon, 09 Dec 2019 10:10:56 PST (-0800), Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 6 +++--- > target/riscv/cpu_bits.h | 12 ++++++------ > 2 files changed, 9 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d23d2cba64..e8ae07107e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -80,14 +80,14 @@ const char * const riscv_excp_names[] = { > const char * const riscv_intr_names[] = { > "u_software", > "s_software", > - "h_software", > + "vs_software", > "m_software", > "u_timer", > "s_timer", > - "h_timer", > + "vs_timer", > "m_timer", > "u_external", > - "s_external", > + "vs_external", > "h_external", > "m_external", > "reserved", > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 9ce73c36de..eeaa03c0f8 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -514,29 +514,29 @@ > /* Interrupt causes */ > #define IRQ_U_SOFT 0 > #define IRQ_S_SOFT 1 > -#define IRQ_H_SOFT 2 /* reserved */ > +#define IRQ_VS_SOFT 2 > #define IRQ_M_SOFT 3 > #define IRQ_U_TIMER 4 > #define IRQ_S_TIMER 5 > -#define IRQ_H_TIMER 6 /* reserved */ > +#define IRQ_VS_TIMER 6 > #define IRQ_M_TIMER 7 > #define IRQ_U_EXT 8 > #define IRQ_S_EXT 9 > -#define IRQ_H_EXT 10 /* reserved */ > +#define IRQ_VS_EXT 10 > #define IRQ_M_EXT 11 > > /* mip masks */ > #define MIP_USIP (1 << IRQ_U_SOFT) > #define MIP_SSIP (1 << IRQ_S_SOFT) > -#define MIP_HSIP (1 << IRQ_H_SOFT) > +#define MIP_VSSIP (1 << IRQ_VS_SOFT) > #define MIP_MSIP (1 << IRQ_M_SOFT) > #define MIP_UTIP (1 << IRQ_U_TIMER) > #define MIP_STIP (1 << IRQ_S_TIMER) > -#define MIP_HTIP (1 << IRQ_H_TIMER) > +#define MIP_VSTIP (1 << IRQ_VS_TIMER) > #define MIP_MTIP (1 << IRQ_M_TIMER) > #define MIP_UEIP (1 << IRQ_U_EXT) > #define MIP_SEIP (1 << IRQ_S_EXT) > -#define MIP_HEIP (1 << IRQ_H_EXT) > +#define MIP_VSEIP (1 << IRQ_VS_EXT) > #define MIP_MEIP (1 << IRQ_M_EXT) > > /* sip masks */ Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d23d2cba64..e8ae07107e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -80,14 +80,14 @@ const char * const riscv_excp_names[] = { const char * const riscv_intr_names[] = { "u_software", "s_software", - "h_software", + "vs_software", "m_software", "u_timer", "s_timer", - "h_timer", + "vs_timer", "m_timer", "u_external", - "s_external", + "vs_external", "h_external", "m_external", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9ce73c36de..eeaa03c0f8 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -514,29 +514,29 @@ /* Interrupt causes */ #define IRQ_U_SOFT 0 #define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 /* reserved */ +#define IRQ_VS_SOFT 2 #define IRQ_M_SOFT 3 #define IRQ_U_TIMER 4 #define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 /* reserved */ +#define IRQ_VS_TIMER 6 #define IRQ_M_TIMER 7 #define IRQ_U_EXT 8 #define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 /* reserved */ +#define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_VSSIP (1 << IRQ_VS_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) #define MIP_UTIP (1 << IRQ_U_TIMER) #define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_VSTIP (1 << IRQ_VS_TIMER) #define MIP_MTIP (1 << IRQ_M_TIMER) #define MIP_UEIP (1 << IRQ_U_EXT) #define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) /* sip masks */
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 6 +++--- target/riscv/cpu_bits.h | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-)