Show patches with: Submitter = Palmer Dabbelt       |    State = Action Required       |    Archived = No       |   12 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,5/5] MAINTAINERS: Add maintainer entry for Goldfish RTC [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes - - 1 - 0 0 0 2020-02-12 Palmer Dabbelt New
[PULL,4/5] riscv: virt: Use Goldfish RTC device [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes 1 - 2 - 0 0 0 2020-02-12 Palmer Dabbelt New
[PULL,3/5] hw: rtc: Add Goldfish RTC device [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes - - 1 - 0 0 0 2020-02-12 Palmer Dabbelt New
[PULL,2/5] riscv: Separate FPU register size from core register size in gdbstub [v2] [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes - - - - 0 0 0 2020-02-12 Palmer Dabbelt New
[PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes - - 1 - 0 0 0 2020-02-12 Palmer Dabbelt New
[PULL,5/5] target/riscv: update mstatus.SD when FS is set dirty [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 2 - 0 0 0 2020-01-21 Palmer Dabbelt New
[PULL,4/5] target/riscv: fsd/fsw doesn't dirty FP state [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 2 - 0 0 0 2020-01-21 Palmer Dabbelt New
[PULL,3/5] target/riscv: Fix tb->flags FS status [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 1 - 0 0 0 2020-01-21 Palmer Dabbelt New
[PULL,2/5] riscv: Set xPIE to 1 after xRET [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 2 1 0 0 0 2020-01-21 Palmer Dabbelt New
[PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 2 - 0 0 0 2020-01-21 Palmer Dabbelt New
[PULL,2/2] hw/riscv: Add optional symbol callback ptr to riscv_load_kernel() [PULL,1/2] RISC-V: virt: This is a "sifive,test1" test finisher - 1 1 - 0 0 0 2019-11-25 Palmer Dabbelt New
[PULL,1/2] RISC-V: virt: This is a "sifive,test1" test finisher [PULL,1/2] RISC-V: virt: This is a "sifive,test1" test finisher - 1 1 - 0 0 0 2019-11-25 Palmer Dabbelt New