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[v1,10/36] target/riscv: Print priv and virt in disas log

Message ID	cb6b09422da8ec4c680889779188c780338a33de.1575914822.git.alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: ES2iYsj0ABSkl8Yuh1yZxgX9GCLus6RCL7IlE94r725XP2kPaPXyNuNLxNkuV3QUW4i4D+JvGh uNJf4iIgf/N8EsWBRHAlV1Cw5oUOIOOLZ6OlDt9JJDQ2qvSEYubUl7v8A4iNVR5iuoDDvIDwVd IRTjSVagXdTF7NRWnrGQQDpvmqeMk4aalPRG3hr23d5A1HQCAGmRIhzULvoibRdb0soRqI1taf DxfymixD4zIc/2PE4j+lzLI03BpbjPojs8UkvYMx5ff5jH879IMTTxulM7frbXaaw0IZkuu34d 5sw= IronPort-SDR: wVkgsR5aYj5UUQ4f1LRS2rZcwlQbKLCTGd8F5dXBl7D0PuRfF9vQrN/TMVBB5mW6S9kpSsQyxB EHxYOwWvrSYCqDxlp0qy8lgNClRW/habj2XYS7pXFBAnTjWz3lWM2x7xFr19egYfVO/kdhA52y MyYISsKIRVAj3BMfmF603v+qPQOA4txiUbk7CJAw0TTq4cOdcthsQNIeAcL/gPvMZin3f4KeXq 4n6GSi6XZPR78HqznnSQhqHW65pVRpRQO1gLEwTq3FlZ8EkO5BtVu2y98iddhheVFaewADxcKC lBPRko402Tg/EERKnUVbl84O IronPort-SDR: szeDcx6Lzw6l7llnfxVAE6Bb8IvmepzqVq/J8bU/USH+MA+zfcpFd/AdFV63l8ZW6J6UxpU92o zSyfwAiyOgdT57Dq38mq5lBn5ummiLwBG4gSmnu8sCKBA7bW8IRS3iEnrdXvPRrCV0vzF1ZFDw MP5QaKweS6CHwtOdTZ9DAy/0iRt+Qa7V0HE/jOOP9VM1Y4Y1x/0WsQaeBGiWrxGjRBcHWvZRtm j6ViWciw5PFK9/JW9BSJ4OV2nsa4/XCHkOZzcItiYhOExPEGHFi/FZCfxIgpaS3IcxGOGr2j6X FVY= WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 10/36] target/riscv: Print priv and virt in disas log Date: Mon, 9 Dec 2019 10:11:06 -0800 Message-Id: <cb6b09422da8ec4c680889779188c780338a33de.1575914822.git.alistair.francis@wdc.com> In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com> References: <cover.1575914822.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Add RISC-V Hypervisor Extension v0.5 \| expand [v1,00/36] Add RISC-V Hypervisor Extension v0.5 [v1,01/36] target/riscv: Convert MIP CSR to target_ulong [v1,02/36] target/riscv: Don't set write permissions on dirty PTEs [v1,03/36] target/riscv: Add the Hypervisor extension [v1,04/36] target/riscv: Add the Hypervisor CSRs to CPUState [v1,05/36] target/riscv: Add support for the new execption numbers [v1,06/36] target/riscv: Rename the H irqs to VS irqs [v1,07/36] target/riscv: Add the virtulisation mode [v1,08/36] target/riscv: Add the force HS exception mode [v1,09/36] target/riscv: Fix CSR perm checking for HS mode [v1,10/36] target/riscv: Print priv and virt in disas log [v1,11/36] target/riscv: Dump Hypervisor registers if enabled [v1,12/36] target/riscv: Add Hypervisor CSR access functions [v1,13/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,14/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,15/36] target/riscv: Convert mstatus to pointers [v1,16/36] target/riscv: Add virtual register swapping function [v1,17/36] target/riscv: Set VS bits in mideleg for Hyp extension [v1,18/36] target/riscv: Extend the MIE CSR to support virtulisation [v1,19/36] target/riscv: Extend the SIP CSR to support virtulisation [v1,20/36] target/riscv: Add support for virtual interrupt setting [v1,21/36] target/ricsv: Flush the TLB on virtulisation mode changes [v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1 [v1,23/36] target/riscv: Add hypvervisor trap support [v1,24/36] target/riscv: Add Hypervisor trap return support [v1,25/36] target/riscv: Add hfence instructions [v1,26/36] target/riscv: Remove the hret instruction [v1,27/36] target/riscv: Disable guest FP support based on virtual status [v1,28/36] target/riscv: Mark both sstatus and vsstatus as dirty [v1,29/36] target/riscv: Respect MPRV and SPRV for floating point ops [v1,30/36] target/riscv: Allow specifying MMU stage [v1,31/36] target/riscv: Implement second stage MMU [v1,32/36] target/riscv: Raise the new execptions when 2nd stage translation fails [v1,33/36] target/riscv: Set htval and mtval2 on execptions [v1,34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR [v1,35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [v1,36/36] target/riscv: Allow enabling the Hypervisor extension

Commit Message

Alistair Francis Dec. 9, 2019, 6:11 p.m. UTC

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/translate.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ab6a891dc3..1a379bd2ae 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -808,7 +808,15 @@  static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 
 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
 {
+#ifndef CONFIG_USER_ONLY
+    RISCVCPU *rvcpu = RISCV_CPU(cpu);
+    CPURISCVState *env = &rvcpu->env;
+#endif
+
     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+#ifndef CONFIG_USER_ONLY
+    qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
+#endif
     log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
 }