| Message ID | c83aac89b3f1825c4c3ae282495a28572031f7d5.1575914822.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V Hypervisor Extension v0.5 | expand |
On Mon, 09 Dec 2019 10:11:48 PST (-0800), Alistair Francis wrote: > The hret instruction does not exist in the new spec versions, so remove > it from QEMU. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/insn32.decode | 1 - > target/riscv/insn_trans/trans_privileged.inc.c | 5 ----- > 2 files changed, 6 deletions(-) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index cfd9ca6d2b..b883672e63 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -75,7 +75,6 @@ ecall 000000000000 00000 000 00000 1110011 > ebreak 000000000001 00000 000 00000 1110011 > uret 0000000 00010 00000 000 00000 1110011 > sret 0001000 00010 00000 000 00000 1110011 > -hret 0010000 00010 00000 000 00000 1110011 > mret 0011000 00010 00000 000 00000 1110011 > wfi 0001000 00101 00000 000 00000 1110011 > hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma > diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c > index b9b5a89b52..76c2fad71c 100644 > --- a/target/riscv/insn_trans/trans_privileged.inc.c > +++ b/target/riscv/insn_trans/trans_privileged.inc.c > @@ -58,11 +58,6 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) > #endif > } > > -static bool trans_hret(DisasContext *ctx, arg_hret *a) > -{ > - return false; > -} > - > static bool trans_mret(DisasContext *ctx, arg_mret *a) > { > #ifndef CONFIG_USER_ONLY Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index cfd9ca6d2b..b883672e63 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -75,7 +75,6 @@ ecall 000000000000 00000 000 00000 1110011 ebreak 000000000001 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 -hret 0010000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c index b9b5a89b52..76c2fad71c 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -58,11 +58,6 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) #endif } -static bool trans_hret(DisasContext *ctx, arg_hret *a) -{ - return false; -} - static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY
The hret instruction does not exist in the new spec versions, so remove it from QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.inc.c | 5 ----- 2 files changed, 6 deletions(-)