Message ID | e89e42f47b337c82ff7fe0ef50986e2df0d7214a.1575914822.git.alistair.francis@wdc.com |
---|---|
State | New |
Headers | show |
Series | Add RISC-V Hypervisor Extension v0.5 | expand |
On Mon, 09 Dec 2019 10:11:22 PST (-0800), Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.h | 10 +++++++ > target/riscv/cpu_bits.h | 7 +++++ > target/riscv/cpu_helper.c | 63 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 80 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 9dc8303c62..eb089fbdb6 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -125,6 +125,7 @@ struct CPURISCVState { > target_ulong *mstatus; > > target_ulong mip; > + > uint32_t miclaim; > > target_ulong mie; > @@ -173,6 +174,14 @@ struct CPURISCVState { > target_ulong mtval2; > target_ulong mtinst; > > + /* HS Backup CSRs */ > + target_ulong stvec_hs; > + target_ulong sscratch_hs; > + target_ulong sepc_hs; > + target_ulong scause_hs; > + target_ulong stval_hs; > + target_ulong satp_hs; > + > target_ulong scounteren; > target_ulong mcounteren; > > @@ -303,6 +312,7 @@ void riscv_cpu_list(void); > #define cpu_mmu_index riscv_cpu_mmu_index > > #ifndef CONFIG_USER_ONLY > +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); > uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index ad6479796c..a24654d137 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -553,4 +553,11 @@ > #define SIP_STIP MIP_STIP > #define SIP_SEIP MIP_SEIP > > +/* MIE masks */ > +#define MIE_SEIE (1 << IRQ_S_EXT) > +#define MIE_UEIE (1 << IRQ_U_EXT) > +#define MIE_STIE (1 << IRQ_S_TIMER) > +#define MIE_UTIE (1 << IRQ_U_TIMER) > +#define MIE_SSIE (1 << IRQ_S_SOFT) > +#define MIE_USIE (1 << IRQ_U_SOFT) > #endif > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 9684da7f7d..63439c9370 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -82,6 +82,69 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) > return false; > } > > +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) > +{ > + target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | > + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; > + bool current_virt = riscv_cpu_virt_enabled(env); > + > + g_assert(riscv_has_ext(env, RVH)); > + > +#if defined(TARGET_RISCV64) > + mstatus_mask |= MSTATUS64_UXL; > +#endif > + > + if (current_virt) { > + /* Current V=1 and we are about to change to V=0 */ > + env->mstatus = &env->mstatus_novirt; > + *env->mstatus &= mstatus_mask; > + *env->mstatus |= env->vsstatus & ~mstatus_mask; > + /* Ensure that vsstatus only holds the correct bits */ > + env->vsstatus &= mstatus_mask; > + > + env->vstvec = env->stvec; > + env->stvec = env->stvec_hs; > + > + env->vsscratch = env->sscratch; > + env->sscratch = env->sscratch_hs; > + > + env->vsepc = env->sepc; > + env->sepc = env->sepc_hs; > + > + env->vscause = env->scause; > + env->scause = env->scause_hs; > + > + env->vstval = env->sbadaddr; > + env->sbadaddr = env->stval_hs; > + > + env->vsatp = env->satp; > + env->satp = env->satp_hs; > + } else { > + /* Current V=0 and we are about to change to V=1 */ > + env->mstatus = &env->vsstatus; > + *env->mstatus &= mstatus_mask; > + *env->mstatus |= env->mstatus_novirt & ~mstatus_mask; > + > + env->stvec_hs = env->stvec; > + env->stvec = env->vstvec; > + > + env->sscratch_hs = env->sscratch; > + env->sscratch = env->vsscratch; > + > + env->sepc_hs = env->sepc; > + env->sepc = env->vsepc; > + > + env->scause_hs = env->scause; > + env->scause = env->vscause; > + > + env->stval_hs = env->sbadaddr; > + env->sbadaddr = env->vstval; > + > + env->satp_hs = env->satp; > + env->satp = env->vsatp; > + } > +} > + > bool riscv_cpu_virt_enabled(CPURISCVState *env) > { > if (!riscv_has_ext(env, RVH)) { Modulo that question about the concept of pointer swapping on the previous patch: Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9dc8303c62..eb089fbdb6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -125,6 +125,7 @@ struct CPURISCVState { target_ulong *mstatus; target_ulong mip; + uint32_t miclaim; target_ulong mie; @@ -173,6 +174,14 @@ struct CPURISCVState { target_ulong mtval2; target_ulong mtinst; + /* HS Backup CSRs */ + target_ulong stvec_hs; + target_ulong sscratch_hs; + target_ulong sepc_hs; + target_ulong scause_hs; + target_ulong stval_hs; + target_ulong satp_hs; + target_ulong scounteren; target_ulong mcounteren; @@ -303,6 +312,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ad6479796c..a24654d137 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -553,4 +553,11 @@ #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP +/* MIE masks */ +#define MIE_SEIE (1 << IRQ_S_EXT) +#define MIE_UEIE (1 << IRQ_U_EXT) +#define MIE_STIE (1 << IRQ_S_TIMER) +#define MIE_UTIE (1 << IRQ_U_TIMER) +#define MIE_SSIE (1 << IRQ_S_SOFT) +#define MIE_USIE (1 << IRQ_U_SOFT) #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9684da7f7d..63439c9370 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -82,6 +82,69 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) +{ + target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + bool current_virt = riscv_cpu_virt_enabled(env); + + g_assert(riscv_has_ext(env, RVH)); + +#if defined(TARGET_RISCV64) + mstatus_mask |= MSTATUS64_UXL; +#endif + + if (current_virt) { + /* Current V=1 and we are about to change to V=0 */ + env->mstatus = &env->mstatus_novirt; + *env->mstatus &= mstatus_mask; + *env->mstatus |= env->vsstatus & ~mstatus_mask; + /* Ensure that vsstatus only holds the correct bits */ + env->vsstatus &= mstatus_mask; + + env->vstvec = env->stvec; + env->stvec = env->stvec_hs; + + env->vsscratch = env->sscratch; + env->sscratch = env->sscratch_hs; + + env->vsepc = env->sepc; + env->sepc = env->sepc_hs; + + env->vscause = env->scause; + env->scause = env->scause_hs; + + env->vstval = env->sbadaddr; + env->sbadaddr = env->stval_hs; + + env->vsatp = env->satp; + env->satp = env->satp_hs; + } else { + /* Current V=0 and we are about to change to V=1 */ + env->mstatus = &env->vsstatus; + *env->mstatus &= mstatus_mask; + *env->mstatus |= env->mstatus_novirt & ~mstatus_mask; + + env->stvec_hs = env->stvec; + env->stvec = env->vstvec; + + env->sscratch_hs = env->sscratch; + env->sscratch = env->vsscratch; + + env->sepc_hs = env->sepc; + env->sepc = env->vsepc; + + env->scause_hs = env->scause; + env->scause = env->vscause; + + env->stval_hs = env->sbadaddr; + env->sbadaddr = env->vstval; + + env->satp_hs = env->satp; + env->satp = env->vsatp; + } +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) {
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.h | 10 +++++++ target/riscv/cpu_bits.h | 7 +++++ target/riscv/cpu_helper.c | 63 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+)