| Message ID | 20190925145750.200592-93-sjg@chromium.org |
|---|---|
| State | Superseded |
| Delegated to: | Bin Meng |
| Headers | show |
| Series | x86: Add initial support for apollolake | expand |
Hi Simon, On Wed, Sep 25, 2019 at 10:59 PM Simon Glass <sjg@chromium.org> wrote: > > These drivers are not needed on all platforms. While they are small, it > is useful in TPL to drop then. Add Kconfig control to allow this. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > drivers/pch/Kconfig | 18 ++++++++++++++++++ > drivers/pch/Makefile | 4 ++-- > 2 files changed, 20 insertions(+), 2 deletions(-) > > diff --git a/drivers/pch/Kconfig b/drivers/pch/Kconfig > index 18f006de24c..a02a1b857cc 100644 > --- a/drivers/pch/Kconfig > +++ b/drivers/pch/Kconfig > @@ -7,3 +7,21 @@ config PCH > northbridge / southbridge architecture that was previously used. The > PCH allows for higher performance since the memory functions are > handled in the CPU. > + > +config X86_PCH7 > + bool "Add support for Intel PCH7" > + default y if X86 > + help > + Enable this if your SoC uses Platform Controller Hub 7 (PCH7). This > + dates from about 2011 and is used on queensbay, for example. The > + PCH proides access to the GPIO and SPI base addresses, among other typo: provides > + functions. > + > +config X86_PCH9 > + bool "Add support for Intel PCH9" > + default y if X86 > + help > + Enable this if your SoC uses Platform Controller Hub 9 (PCH9). This > + dates from about 2015 and is used on queensbay, for example. The used on baytrail, I think > + PCH proides access to the GPIO and SPI base addresses, among other typo: provides > + functions. > diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile > index 8ea6b7852ac..d5de3e48be1 100644 > --- a/drivers/pch/Makefile > +++ b/drivers/pch/Makefile > @@ -1,6 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0+ > > obj-y += pch-uclass.o > -obj-y += pch7.o > -obj-y += pch9.o > +obj-$(CONFIG_X86_PCH7) += pch7.o > +obj-$(CONFIG_X86_PCH9) += pch9.o > obj-$(CONFIG_SANDBOX) += sandbox_pch.o > -- Other than above, Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/drivers/pch/Kconfig b/drivers/pch/Kconfig index 18f006de24c..a02a1b857cc 100644 --- a/drivers/pch/Kconfig +++ b/drivers/pch/Kconfig @@ -7,3 +7,21 @@ config PCH northbridge / southbridge architecture that was previously used. The PCH allows for higher performance since the memory functions are handled in the CPU. + +config X86_PCH7 + bool "Add support for Intel PCH7" + default y if X86 + help + Enable this if your SoC uses Platform Controller Hub 7 (PCH7). This + dates from about 2011 and is used on queensbay, for example. The + PCH proides access to the GPIO and SPI base addresses, among other + functions. + +config X86_PCH9 + bool "Add support for Intel PCH9" + default y if X86 + help + Enable this if your SoC uses Platform Controller Hub 9 (PCH9). This + dates from about 2015 and is used on queensbay, for example. The + PCH proides access to the GPIO and SPI base addresses, among other + functions. diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile index 8ea6b7852ac..d5de3e48be1 100644 --- a/drivers/pch/Makefile +++ b/drivers/pch/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += pch-uclass.o -obj-y += pch7.o -obj-y += pch9.o +obj-$(CONFIG_X86_PCH7) += pch7.o +obj-$(CONFIG_X86_PCH9) += pch9.o obj-$(CONFIG_SANDBOX) += sandbox_pch.o
These drivers are not needed on all platforms. While they are small, it is useful in TPL to drop then. Add Kconfig control to allow this. Signed-off-by: Simon Glass <sjg@chromium.org> --- drivers/pch/Kconfig | 18 ++++++++++++++++++ drivers/pch/Makefile | 4 ++-- 2 files changed, 20 insertions(+), 2 deletions(-)