diff mbox series

[U-Boot,088/126] x86: Set the DRAM banks to reflect real location

Message ID 20190925145750.200592-89-sjg@chromium.org
State Superseded
Delegated to: Bin Meng
Headers show
Series x86: Add initial support for apollolake | expand

Commit Message

Simon Glass Sept. 25, 2019, 2:57 p.m. UTC 
At present with fsp a single DRAM bank is added which extends to the
whole size of memory. However there is typically only 2GB of memory
available below the 4GB boundary, and this is what is used by U-Boot while
running in 32-bit mode.

Scan the tables to set the banks correct. The first bank is set to memory
below 4GB, and the rest of memory is put into subsequent banks.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/lib/fsp/fsp_dram.c | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

Comments

Bin Meng Oct. 10, 2019, 9:03 a.m. UTC | #1 
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass <sjg@chromium.org> wrote:
>
> At present with fsp a single DRAM bank is added which extends to the
> whole size of memory. However there is typically only 2GB of memory
> available below the 4GB boundary, and this is what is used by U-Boot while
> running in 32-bit mode.
>
> Scan the tables to set the banks correct. The first bank is set to memory
> below 4GB, and the rest of memory is put into subsequent banks.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/lib/fsp/fsp_dram.c | 32 +++++++++++++++++++++++++++++++-
>  1 file changed, 31 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 38cc25839ec..9161af65b98 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -37,8 +37,38 @@  int fsp_scan_for_ram_size(void)
 
 int dram_init_banksize(void)
 {
+	const struct hob_header *hdr;
+	struct hob_res_desc *res_desc;
+	phys_addr_t low_end;
+	uint bank;
+
+	low_end = 0;
+	for (bank = 1, hdr = gd->arch.hob_list;
+	     bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
+	     hdr = get_next_hob(hdr)) {
+		if (hdr->type != HOB_TYPE_RES_DESC)
+			continue;
+		res_desc = (struct hob_res_desc *)hdr;
+		if (res_desc->type != RES_SYS_MEM &&
+		    res_desc->type != RES_MEM_RESERVED)
+			continue;
+		if (res_desc->phys_start < (1ULL << 32)) {
+			low_end = max(low_end,
+				      res_desc->phys_start + res_desc->len);
+			continue;
+		}
+
+		gd->bd->bi_dram[bank].start = res_desc->phys_start;
+		gd->bd->bi_dram[bank].size = res_desc->len;
+		mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
+				 res_desc->len);
+		log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
+			  gd->bd->bi_dram[bank].size);
+	}
+
+	/* Add the memory below 4GB */
 	gd->bd->bi_dram[0].start = 0;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->bd->bi_dram[0].size = low_end;
 
 	return 0;
 }