diff mbox series

[U-Boot,065/126] x86: Use mtrr_commit() with FSP2

Message ID 20190925145750.200592-66-sjg@chromium.org
State Accepted
Commit cc2d27dcdc3e1c76d09d54015e3992380bd7e0fa
Delegated to: Bin Meng
Headers show
Series x86: Add initial support for apollolake | expand

Commit Message

Simon Glass Sept. 25, 2019, 2:56 p.m. UTC
With FSP2 we use MTRRs in U-Boot proper even though the 32-bit init
happens in TPL. Enable this, using a variable to try to make the
conditions more palatable.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/lib/init_helpers.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

Comments

Bin Meng Oct. 7, 2019, 1:53 p.m. UTC | #1
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass <sjg@chromium.org> wrote:
>
> With FSP2 we use MTRRs in U-Boot proper even though the 32-bit init
> happens in TPL. Enable this, using a variable to try to make the
> conditions more palatable.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/lib/init_helpers.c | 22 +++++++++++++++-------
>  1 file changed, 15 insertions(+), 7 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng Oct. 7, 2019, 2:09 p.m. UTC | #2
On Mon, Oct 7, 2019 at 9:53 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, Sep 25, 2019 at 10:58 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > With FSP2 we use MTRRs in U-Boot proper even though the 32-bit init
> > happens in TPL. Enable this, using a variable to try to make the
> > conditions more palatable.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  arch/x86/lib/init_helpers.c | 22 +++++++++++++++-------
> >  1 file changed, 15 insertions(+), 7 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!
diff mbox series

Patch

diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 4774a9bdb78..3e3a11ac2fa 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -12,15 +12,23 @@  DECLARE_GLOBAL_DATA_PTR;
 
 int init_cache_f_r(void)
 {
-#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) && \
-		!defined(CONFIG_SYS_SLIMBOOTLOADER)
+	bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
+		 IS_ENABLED(CONFIG_FSP_VERSION2);
 	int ret;
 
-	ret = mtrr_commit(false);
-	/* If MTRR MSR is not implemented by the processor, just ignore it */
-	if (ret && ret != -ENOSYS)
-		return ret;
-#endif
+	do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
+		!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
+
+	if (do_mtrr) {
+		ret = mtrr_commit(false);
+		/*
+		 * If MTRR MSR is not implemented by the processor, just ignore
+		 * it
+		 */
+		if (ret && ret != -ENOSYS)
+			return ret;
+	}
+
 	/* Initialise the CPU cache(s) */
 	return init_cache();
 }