Show patches with: Submitter = Bin Meng       |    State = Action Required       |    Archived = No       |   25 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[U-Boot,v5,25/25] riscv: Remove ae350.dts riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,24/25] riscv: bootm: Change to use boot_hart from global data riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,23/25] riscv: Save boot hart id to the global data riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,22/25] riscv: Adjust the _exit_trap() position to come before handle_trap() riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,21/25] riscv: Return to previous privilege level after trap handling riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,20/25] riscv: Fix context restore before returning from trap handler riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,19/25] riscv: Move trap handler codes to mtrap.S riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,18/25] riscv: Do some basic architecture level cpu initialization riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,17/25] riscv: Add indirect stringification to csr_xxx ops riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,16/25] riscv: Update supports_extension() to use desc from cpu driver riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,15/25] riscv: Add exception codes for xcause register riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,14/25] riscv: Add CSR numbers riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,13/25] riscv: Remove non-DM version of print_cpuinfo() riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,12/25] riscv: Probe cpus during boot riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,11/25] riscv: Enlarge the default SYS_MALLOC_F_LEN riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,10/25] riscv: qemu: Add platform-specific Kconfig options riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,09/25] riscv: Implement riscv_get_time() API using rdtime instruction riscv: Adding RISC-V CPU and timer driver - - 1 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,08/25] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,07/25] riscv: Introduce a Kconfig option for machine mode riscv: Adding RISC-V CPU and timer driver - - 1 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,06/25] riscv: ax25: Hide the ax25-specific Kconfig option riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,05/25] timer: Add generic driver for RISC-V privileged architecture defined timer riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,04/25] cpu: Add a RISC-V CPU driver riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,03/25] riscv: qemu: Create a simple-bus driver for the soc node riscv: Adding RISC-V CPU and timer driver - - 2 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,02/25] dm: cpu: Add timebase frequency to the platdata riscv: Adding RISC-V CPU and timer driver - - 3 - 0 0 0 2018-12-12 Bin Meng Andes New
[U-Boot,v5,01/25] riscv: add Kconfig entries for the code model riscv: Adding RISC-V CPU and timer driver - - 1 - 0 0 0 2018-12-12 Bin Meng Andes New