diff mbox series

[U-Boot,079/126] x86: Reduce mrccache record alignment size

Message ID 20190925145750.200592-80-sjg@chromium.org
State Superseded
Delegated to: Bin Meng
Headers show
Series x86: Add initial support for apollolake | expand

Commit Message

Simon Glass Sept. 25, 2019, 2:57 p.m. UTC
At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollolake's 24-byte variable-data record.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/mrccache.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Bin Meng Oct. 10, 2019, 5:09 a.m. UTC | #1
Hi Simon,

On Wed, Sep 25, 2019 at 10:59 PM Simon Glass <sjg@chromium.org> wrote:
>
> At present the records are 4KB in size. This is unnecessarily large when
> the SPI-flash erase size is 256 bytes. Reduce it so it will be more

But this will break for SPI-flash erase size that is not 256 bytes?

> efficient with Apollolake's 24-byte variable-data record.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/mrccache.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Regards,
Bin
Simon Glass Oct. 10, 2019, 5:06 p.m. UTC | #2
Hi Bin,

On Wed, 9 Oct 2019 at 23:09, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Wed, Sep 25, 2019 at 10:59 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present the records are 4KB in size. This is unnecessarily large when
> > the SPI-flash erase size is 256 bytes. Reduce it so it will be more
>
> But this will break for SPI-flash erase size that is not 256 bytes?

The way it works is that it erases the whole region, then fills it up
record by record, then when it gets full, erases it all again. So I
think it is OK.

Regards,
Simon
diff mbox series

Patch

diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h
index 40fda856ff4..abf58182237 100644
--- a/arch/x86/include/asm/mrccache.h
+++ b/arch/x86/include/asm/mrccache.h
@@ -7,7 +7,7 @@ 
 #ifndef _ASM_MRCCACHE_H
 #define _ASM_MRCCACHE_H
 
-#define MRC_DATA_ALIGN		0x1000
+#define MRC_DATA_ALIGN		0x100
 #define MRC_DATA_SIGNATURE	(('M' << 0) | ('R' << 8) | \
 				 ('C' << 16) | ('D'<<24))