diff mbox series

[U-Boot,29/47] P2041: dts: Added PCIe DT nodes

Message ID 20190723130938.47805-30-Zhiqiang.Hou@nxp.com
State Superseded
Delegated to: Prabhakar Kushwaha
Headers show
Series powerpc: Enable PCIe DM drvier for some platforms | expand

Commit Message

Z.Q. Hou July 23, 2019, 1:09 p.m. UTC 
P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/p2041.dtsi | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

Comments

Bin Meng Aug. 26, 2019, 2:49 p.m. UTC | #1 
On Tue, Jul 23, 2019 at 9:28 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P2041 integrated 3 PCIe controllers, which is compatible with
> the PCI Express™ Base Specification, Revision 2.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p2041.dtsi | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
index 9aa0422..55f7adc 100644
--- a/arch/powerpc/dts/p2041.dtsi
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -60,4 +60,40 @@ 
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie@ffe200000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe201000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe202000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };