diff mbox series

[U-Boot,46/47] powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled

Message ID 20190723130938.47805-47-Zhiqiang.Hou@nxp.com
State Superseded
Delegated to: Prabhakar Kushwaha
Headers show
Series powerpc: Enable PCIe DM drvier for some platforms | expand

Commit Message

Z.Q. Hou July 23, 2019, 1:09 p.m. UTC 
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/MPC8548CDS.h | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

Comments

Bin Meng Aug. 26, 2019, 2:50 p.m. UTC | #1 
On Tue, Jul 23, 2019 at 9:28 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/MPC8548CDS.h | 22 ++++++++++++++--------
>  1 file changed, 14 insertions(+), 8 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 4252fbe..4809bbd 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -18,8 +18,6 @@ 
 #define CONFIG_PCI1		/* PCI controller 1 */
 #define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
 #undef CONFIG_PCI2
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -343,24 +341,18 @@  extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_NAME		"Slot"
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
 #endif
 
 /*
@@ -386,6 +378,20 @@  extern unsigned long get_clock_freq(void);
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT		1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	1
+#define CONFIG_SYS_PCIE1_NAME		"Slot"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
+#endif
+
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
 #endif	/* CONFIG_PCI */