| Message ID | 20190723130938.47805-14-Zhiqiang.Hou@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | Prabhakar Kushwaha |
| Headers | show |
| Series | powerpc: Enable PCIe DM drvier for some platforms | expand |
Hi Zhiqiang, On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote: > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > include/configs/T102xRDB.h | 54 +++++++++++++--------------------------------- > 1 file changed, 15 insertions(+), 39 deletions(-) > > diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h > index 3715e25..4fb1709 100644 > --- a/include/configs/T102xRDB.h > +++ b/include/configs/T102xRDB.h > @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void); > #define CONFIG_PCIE1 /* PCIE controller 1 */ > #define CONFIG_PCIE2 /* PCIE controller 2 */ > #define CONFIG_PCIE3 /* PCIE controller 3 */ > -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ > -#define CONFIG_PCI_INDIRECT_BRIDGE > > #ifdef CONFIG_PCI > /* controller 1, direct to uli, tgtid 3, Base address 20000 */ > #ifdef CONFIG_PCIE1 > #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 > -#ifdef CONFIG_PHYS_64BIT > -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 > #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull > -#else > -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 > -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 > -#endif > -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ > #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 > -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 > -#ifdef CONFIG_PHYS_64BIT > #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull > -#else > -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 > -#endif > -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ > #endif > > /* controller 2, Slot 2, tgtid 2, Base address 201000 */ > #ifdef CONFIG_PCIE2 > #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 > -#ifdef CONFIG_PHYS_64BIT > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 > #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull > -#else > -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 > -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 > -#endif > -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ > #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 > -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 > -#ifdef CONFIG_PHYS_64BIT > #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull > -#else > -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 > -#endif > -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ > #endif > > /* controller 3, Slot 1, tgtid 1, Base address 202000 */ > #ifdef CONFIG_PCIE3 > #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 > -#ifdef CONFIG_PHYS_64BIT > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 > #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull > -#else > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 > -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 > -#endif > -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ > #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 > -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 > -#ifdef CONFIG_PHYS_64BIT > #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull > -#else > -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 > #endif > + > +#if !defined(CONFIG_DM_PCI) > +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 What about the #ifdef CONFIG_PHYS_64BIT part? > +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ > +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 > +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 > +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ > +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 > +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ > +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 > +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ > +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 > #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ > +#define CONFIG_PCI_INDIRECT_BRIDGE > #endif > > #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ > -- Regards, Bin
Hi Bin, Thanks a lot for your comments! > -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 2019年8月26日 22:49 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com> > Subject: Re: [U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy > PCIe driver when DM_PCI is enabled > > Hi Zhiqiang, > > On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > wrote: > > > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > include/configs/T102xRDB.h | 54 > > +++++++++++++--------------------------------- > > 1 file changed, 15 insertions(+), 39 deletions(-) > > > > diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h > > index 3715e25..4fb1709 100644 > > --- a/include/configs/T102xRDB.h > > +++ b/include/configs/T102xRDB.h > > @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void); > > #define CONFIG_PCIE1 /* PCIE controller 1 */ > > #define CONFIG_PCIE2 /* PCIE controller 2 */ > > #define CONFIG_PCIE3 /* PCIE controller 3 */ > > -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > > #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ > > -#define CONFIG_PCI_INDIRECT_BRIDGE > > > > #ifdef CONFIG_PCI > > /* controller 1, direct to uli, tgtid 3, Base address 20000 */ > > #ifdef CONFIG_PCIE1 > > #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 > > #define CONFIG_SYS_PCIE1_MEM_PHYS > 0xc00000000ull > > -#else > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 > > -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 > > -#endif > > -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* > 256M */ > > #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 > > -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull > > -#else > > -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 > > -#endif > > -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ > > #endif > > > > /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef > > CONFIG_PCIE2 > > #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 > > #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull > > -#else > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 > > -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 > > -#endif > > -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* > 256M */ > > #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 > > -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull > > -#else > > -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 > > -#endif > > -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ > > #endif > > > > /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef > > CONFIG_PCIE3 > > #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 > > #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull > > -#else > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 > > -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 > > -#endif > > -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* > 256M */ > > #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 > > -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull > > -#else > > -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 > > #endif > > + > > +#if !defined(CONFIG_DM_PCI) > > +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 > > What about the #ifdef CONFIG_PHYS_64BIT part? In the arch/powerpc/cpu/mpc85xx/Kconfig, all the T102x boards selected the CONFIG_PHYS_64BIT, so removed the #else...#endif part. Thanks, Zhiqiang > > > +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* > 256M */ > > +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 > > +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ > > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 > > +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ > > +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 > > +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ > > +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 > > +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* > 256M */ > > +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 > > #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k > */ > > +#define CONFIG_PCI_INDIRECT_BRIDGE > > #endif > > > > #define CONFIG_PCI_SCAN_SHOW /* show pci devices on > startup */ > > -- > > Regards, > Bin
Hi Zhiqiang, On Tue, Aug 27, 2019 at 10:33 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote: > > Hi Bin, > > Thanks a lot for your comments! > > > -----Original Message----- > > From: Bin Meng <bmeng.cn@gmail.com> > > Sent: 2019年8月26日 22:49 > > To: Z.q. Hou <zhiqiang.hou@nxp.com> > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha > > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka > > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com> > > Subject: Re: [U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy > > PCIe driver when DM_PCI is enabled > > > > Hi Zhiqiang, > > > > On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > wrote: > > > > > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > --- > > > include/configs/T102xRDB.h | 54 > > > +++++++++++++--------------------------------- > > > 1 file changed, 15 insertions(+), 39 deletions(-) > > > > > > diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h > > > index 3715e25..4fb1709 100644 > > > --- a/include/configs/T102xRDB.h > > > +++ b/include/configs/T102xRDB.h > > > @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void); > > > #define CONFIG_PCIE1 /* PCIE controller 1 */ > > > #define CONFIG_PCIE2 /* PCIE controller 2 */ > > > #define CONFIG_PCIE3 /* PCIE controller 3 */ > > > -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > > > #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ > > > -#define CONFIG_PCI_INDIRECT_BRIDGE > > > > > > #ifdef CONFIG_PCI > > > /* controller 1, direct to uli, tgtid 3, Base address 20000 */ > > > #ifdef CONFIG_PCIE1 > > > #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 > > > -#ifdef CONFIG_PHYS_64BIT > > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 > > > #define CONFIG_SYS_PCIE1_MEM_PHYS > > 0xc00000000ull > > > -#else > > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 > > > -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 > > > -#endif > > > -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* > > 256M */ > > > #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 > > > -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 > > > -#ifdef CONFIG_PHYS_64BIT > > > #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull > > > -#else > > > -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 > > > -#endif > > > -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ > > > #endif > > > > > > /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef > > > CONFIG_PCIE2 > > > #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 > > > -#ifdef CONFIG_PHYS_64BIT > > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 > > > #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull > > > -#else > > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 > > > -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 > > > -#endif > > > -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* > > 256M */ > > > #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 > > > -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 > > > -#ifdef CONFIG_PHYS_64BIT > > > #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull > > > -#else > > > -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 > > > -#endif > > > -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ > > > #endif > > > > > > /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef > > > CONFIG_PCIE3 > > > #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 > > > -#ifdef CONFIG_PHYS_64BIT > > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 > > > #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull > > > -#else > > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 > > > -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 > > > -#endif > > > -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* > > 256M */ > > > #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 > > > -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 > > > -#ifdef CONFIG_PHYS_64BIT > > > #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull > > > -#else > > > -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 > > > #endif > > > + > > > +#if !defined(CONFIG_DM_PCI) > > > +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > > > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 > > > > What about the #ifdef CONFIG_PHYS_64BIT part? > > In the arch/powerpc/cpu/mpc85xx/Kconfig, all the T102x boards selected > the CONFIG_PHYS_64BIT, so removed the #else...#endif part. > Thanks for the clarification. With that info, Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Regards, Bin
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 3715e25..4fb1709 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- include/configs/T102xRDB.h | 54 +++++++++++++--------------------------------- 1 file changed, 15 insertions(+), 39 deletions(-)