| Message ID | 20190723130938.47805-26-Zhiqiang.Hou@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | Prabhakar Kushwaha |
| Headers | show |
| Series | powerpc: Enable PCIe DM drvier for some platforms | expand |
On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote: > > P2020 integrated 3 PCIe controllers, which is compatible with > the PCI Express™ Base Specification, Revision 1.0a, and this > patch is to add DT node for each PCIe controller. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > arch/powerpc/dts/p2020-post.dtsi | 30 ++++++++++++++++++++++++++++++ > arch/powerpc/dts/p2020rdb-pc.dts | 17 +++++++++++++++++ > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++ > 3 files changed, 64 insertions(+) > > diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi > index f20d1fa..f696f35 100644 > --- a/arch/powerpc/dts/p2020-post.dtsi > +++ b/arch/powerpc/dts/p2020-post.dtsi > @@ -25,3 +25,33 @@ > last-interrupt-source = <255>; > }; > }; > + > +/* PCIe controller base address 0x8000 */ > +&pci2 { pci0? > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; > + law_trgt_if = <0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + bus-range = <0x0 0xff>; > +}; > + > +/* PCIe controller base address 0x9000 */ > +&pci1 { > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; > + law_trgt_if = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + bus-range = <0x0 0xff>; > +}; > + > +/* PCIe controller base address 0xa000 */ > +&pci0 { pci2? > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; > + law_trgt_if = <2>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + bus-range = <0x0 0xff>; > +}; > diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts > index 4800b76..08befd4 100644 > --- a/arch/powerpc/dts/p2020rdb-pc.dts > +++ b/arch/powerpc/dts/p2020rdb-pc.dts > @@ -18,6 +18,23 @@ > soc: soc@ffe00000 { > ranges = <0x0 0x0 0xffe00000 0x100000>; > }; > + > + pci2: pcie@ffe08000 { > + reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */ put <reg> in dtsi? > + status = "disabled"; > + }; > + > + pci1: pcie@ffe09000 { > + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ > + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ > + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ > + }; > + > + pci0: pcie@ffe0a000 { > + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ > + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ > + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ > + }; > }; > > /include/ "p2020-post.dtsi" > diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts > index 8323b90..04b2519 100644 > --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts > +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts > @@ -18,6 +18,23 @@ > soc: soc@fffe00000 { > ranges = <0x0 0xf 0xffe00000 0x100000>; > }; > + > + pci2: pcie@fffe08000 { > + reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */ > + status = "disabled"; > + }; > + > + pci1: pcie@fffe09000 { > + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */ > + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */ > + 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ > + }; > + > + pci0: pcie@fffe0a000 { > + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */ > + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ > + 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ > + }; > }; > > /include/ "p2020-post.dtsi" > -- Regards, Bin
Hi Bin, Thanks a lot for your comments! > -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 2019年8月26日 22:50 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com> > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes > > On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > wrote: > > > > P2020 integrated 3 PCIe controllers, which is compatible with the PCI > > Express™ Base Specification, Revision 1.0a, and this patch is to add > > DT node for each PCIe controller. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > arch/powerpc/dts/p2020-post.dtsi | 30 > ++++++++++++++++++++++++++++++ > > arch/powerpc/dts/p2020rdb-pc.dts | 17 +++++++++++++++++ > > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++ > > 3 files changed, 64 insertions(+) > > > > diff --git a/arch/powerpc/dts/p2020-post.dtsi > > b/arch/powerpc/dts/p2020-post.dtsi > > index f20d1fa..f696f35 100644 > > --- a/arch/powerpc/dts/p2020-post.dtsi > > +++ b/arch/powerpc/dts/p2020-post.dtsi > > @@ -25,3 +25,33 @@ > > last-interrupt-source = <255>; > > }; > > }; > > + > > +/* PCIe controller base address 0x8000 */ > > +&pci2 { > > pci0? Describe the controller index and starting address according to P2020 RM. > > > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; > > + law_trgt_if = <0>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + bus-range = <0x0 0xff>; > > +}; > > + > > +/* PCIe controller base address 0x9000 */ > > +&pci1 { > > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; > > + law_trgt_if = <1>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + bus-range = <0x0 0xff>; > > +}; > > + > > +/* PCIe controller base address 0xa000 */ > > +&pci0 { > > pci2? > > > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; > > + law_trgt_if = <2>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + bus-range = <0x0 0xff>; > > +}; > > diff --git a/arch/powerpc/dts/p2020rdb-pc.dts > > b/arch/powerpc/dts/p2020rdb-pc.dts > > index 4800b76..08befd4 100644 > > --- a/arch/powerpc/dts/p2020rdb-pc.dts > > +++ b/arch/powerpc/dts/p2020rdb-pc.dts > > @@ -18,6 +18,23 @@ > > soc: soc@ffe00000 { > > ranges = <0x0 0x0 0xffe00000 0x100000>; > > }; > > + > > + pci2: pcie@ffe08000 { > > + reg = <0x0 0xffe08000 0x0 0x1000>; /* registers > */ > > put <reg> in dtsi? The same reason as P1020, see #22 of this series. Thanks, Zhiqiang > > > + status = "disabled"; > > + }; > > + > > + pci1: pcie@ffe09000 { > > + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers > */ > > + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 > 0x0 0x00010000 /* downstream I/O */ > > + 0x02000000 0x0 0xa0000000 0x0 > 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ > > + }; > > + > > + pci0: pcie@ffe0a000 { > > + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers > */ > > + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 > 0x0 0x00010000 /* downstream I/O */ > > + 0x02000000 0x0 0x80000000 0x0 > 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ > > + }; > > }; > > > > /include/ "p2020-post.dtsi" > > diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts > > b/arch/powerpc/dts/p2020rdb-pc_36b.dts > > index 8323b90..04b2519 100644 > > --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts > > +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts > > @@ -18,6 +18,23 @@ > > soc: soc@fffe00000 { > > ranges = <0x0 0xf 0xffe00000 0x100000>; > > }; > > + > > + pci2: pcie@fffe08000 { > > + reg = <0xf 0xffe08000 0x0 0x1000>; /* registers > */ > > + status = "disabled"; > > + }; > > + > > + pci1: pcie@fffe09000 { > > + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers > */ > > + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 > 0x0 0x00010000 /* downstream I/O */ > > + 0x02000000 0x0 0xc0000000 0xc > 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ > > + }; > > + > > + pci0: pcie@fffe0a000 { > > + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers > */ > > + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 > 0x0 0x00010000 /* downstream I/O */ > > + 0x02000000 0x0 0x80000000 0xc > 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ > > + }; > > }; > > > > /include/ "p2020-post.dtsi" > > -- > > Regards, > Bin
Hi Zhiqiang, On Tue, Aug 27, 2019 at 10:52 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote: > > Hi Bin, > > Thanks a lot for your comments! > > > -----Original Message----- > > From: Bin Meng <bmeng.cn@gmail.com> > > Sent: 2019年8月26日 22:50 > > To: Z.q. Hou <zhiqiang.hou@nxp.com> > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha > > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka > > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com> > > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes > > > > On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > wrote: > > > > > > P2020 integrated 3 PCIe controllers, which is compatible with the PCI > > > Express™ Base Specification, Revision 1.0a, and this patch is to add > > > DT node for each PCIe controller. > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > --- > > > arch/powerpc/dts/p2020-post.dtsi | 30 > > ++++++++++++++++++++++++++++++ > > > arch/powerpc/dts/p2020rdb-pc.dts | 17 +++++++++++++++++ > > > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++ > > > 3 files changed, 64 insertions(+) > > > > > > diff --git a/arch/powerpc/dts/p2020-post.dtsi > > > b/arch/powerpc/dts/p2020-post.dtsi > > > index f20d1fa..f696f35 100644 > > > --- a/arch/powerpc/dts/p2020-post.dtsi > > > +++ b/arch/powerpc/dts/p2020-post.dtsi > > > @@ -25,3 +25,33 @@ > > > last-interrupt-source = <255>; > > > }; > > > }; > > > + > > > +/* PCIe controller base address 0x8000 */ > > > +&pci2 { > > > > pci0? > > Describe the controller index and starting address according to P2020 RM. OK, so will this weird index number (2, 1, 0) break the index calculation log in the following patch? http://patchwork.ozlabs.org/patch/1152811/ Regards, Bin
Hi Bin, > -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 2019年8月27日 10:56 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com> > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes > > Hi Zhiqiang, > > On Tue, Aug 27, 2019 at 10:52 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote: > > > > Hi Bin, > > > > Thanks a lot for your comments! > > > > > -----Original Message----- > > > From: Bin Meng <bmeng.cn@gmail.com> > > > Sent: 2019年8月26日 22:50 > > > To: Z.q. Hou <zhiqiang.hou@nxp.com> > > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha > > > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; > Priyanka > > > Jain <priyanka.jain@nxp.com>; Shengzhou Liu > <shengzhou.liu@nxp.com> > > > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes > > > > > > On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > wrote: > > > > > > > > P2020 integrated 3 PCIe controllers, which is compatible with the > > > > PCI Express™ Base Specification, Revision 1.0a, and this patch is > > > > to add DT node for each PCIe controller. > > > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > --- > > > > arch/powerpc/dts/p2020-post.dtsi | 30 > > > ++++++++++++++++++++++++++++++ > > > > arch/powerpc/dts/p2020rdb-pc.dts | 17 +++++++++++++++++ > > > > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++ > > > > 3 files changed, 64 insertions(+) > > > > > > > > diff --git a/arch/powerpc/dts/p2020-post.dtsi > > > > b/arch/powerpc/dts/p2020-post.dtsi > > > > index f20d1fa..f696f35 100644 > > > > --- a/arch/powerpc/dts/p2020-post.dtsi > > > > +++ b/arch/powerpc/dts/p2020-post.dtsi > > > > @@ -25,3 +25,33 @@ > > > > last-interrupt-source = <255>; > > > > }; > > > > }; > > > > + > > > > +/* PCIe controller base address 0x8000 */ > > > > +&pci2 { > > > > > > pci0? > > > > Describe the controller index and starting address according to P2020 RM. > > OK, so will this weird index number (2, 1, 0) break the index calculation log in > the following patch? No, the code handled this. Thanks, Zhiqiang > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch > work.ozlabs.org%2Fpatch%2F1152811%2F&data=02%7C01%7Czhiqian > g.hou%40nxp.com%7Cb20f64bf19f445e50ce108d72a9a160a%7C686ea1d3b > c2b4c6fa92cd99c5c301635%7C0%7C0%7C637024713598549064&sdat > a=WG5PXoeY0zriaxdITqzOJ%2BnT65uzrQ%2FUtwi4JuykXnA%3D&reser > ved=0 > > Regards, > Bin
On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote: > > P2020 integrated 3 PCIe controllers, which is compatible with > the PCI Express™ Base Specification, Revision 1.0a, and this > patch is to add DT node for each PCIe controller. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > arch/powerpc/dts/p2020-post.dtsi | 30 ++++++++++++++++++++++++++++++ > arch/powerpc/dts/p2020rdb-pc.dts | 17 +++++++++++++++++ > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++ > 3 files changed, 64 insertions(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index f20d1fa..f696f35 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -25,3 +25,33 @@ last-interrupt-source = <255>; }; }; + +/* PCIe controller base address 0x8000 */ +&pci2 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 4800b76..08befd4 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -18,6 +18,23 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; + + pci2: pcie@ffe08000 { + reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */ + status = "disabled"; + }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 8323b90..04b2519 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -18,6 +18,23 @@ soc: soc@fffe00000 { ranges = <0x0 0xf 0xffe00000 0x100000>; }; + + pci2: pcie@fffe08000 { + reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */ + status = "disabled"; + }; + + pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "p2020-post.dtsi"
P2020 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- arch/powerpc/dts/p2020-post.dtsi | 30 ++++++++++++++++++++++++++++++ arch/powerpc/dts/p2020rdb-pc.dts | 17 +++++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++ 3 files changed, 64 insertions(+)