| Message ID | 8dae4338c8938696dfcecee6e736f6b09cc82877.1566603412.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V Hypervisor Extension v0.4 | expand |
On Fri, 23 Aug 2019 16:39:03 PDT (-0700), Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 5 +++++ > target/riscv/cpu.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 06ee551ebe..39e1c130df 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -447,6 +447,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (cpu->cfg.ext_u) { > target_misa |= RVU; > } > + if (cpu->cfg.ext_h) { > + target_misa |= RVH; > + } > > set_misa(env, RVXLEN | target_misa); > } > @@ -493,6 +496,8 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > + /* This is experimental so mark with 'x-' */ > + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b63f1f3cdc..500496a3be 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -268,6 +268,7 @@ typedef struct RISCVCPU { > bool ext_c; > bool ext_s; > bool ext_u; > + bool ext_h; > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 06ee551ebe..39e1c130df 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -447,6 +447,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_u) { target_misa |= RVU; } + if (cpu->cfg.ext_h) { + target_misa |= RVH; + } set_misa(env, RVXLEN | target_misa); } @@ -493,6 +496,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b63f1f3cdc..500496a3be 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -268,6 +268,7 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_h; bool ext_counters; bool ext_ifencei; bool ext_icsr;
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+)