Message ID | 2b2e042b3c80d4f37cf150853a0a040581feb403.1566603412.git.alistair.francis@wdc.com |
---|---|
State | New |
Headers | show |
Series | Add RISC-V Hypervisor Extension v0.4 | expand |
On Fri, 23 Aug 2019 16:38:29 PDT (-0700), Alistair Francis wrote: > When the PLIC generates an interrupt ensure we always set it for the SIP > CSR that corresponds to the HS (V=0) register. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_plic.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c > index 98e4304b66..8309e96f64 100644 > --- a/hw/riscv/sifive_plic.c > +++ b/hw/riscv/sifive_plic.c > @@ -150,7 +150,17 @@ static void sifive_plic_update(SiFivePLICState *plic) > riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)); > break; > case PLICMode_S: > - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); > + if (riscv_cpu_virt_enabled(env)) { > + if (level) { > + atomic_or(&env->mip_novirt, MIP_SEIP); > + g_assert(riscv_cpu_virt_enabled(env)); > + } else { > + atomic_and(&env->mip_novirt, ~MIP_SEIP); > + g_assert(riscv_cpu_virt_enabled(env)); > + } > + } else { > + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); > + } > break; > default: > break; This is going to go when we change the interrupt delivery mechanism.
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 98e4304b66..8309e96f64 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -150,7 +150,17 @@ static void sifive_plic_update(SiFivePLICState *plic) riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)); break; case PLICMode_S: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + if (riscv_cpu_virt_enabled(env)) { + if (level) { + atomic_or(&env->mip_novirt, MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } else { + atomic_and(&env->mip_novirt, ~MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } + } else { + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + } break; default: break;
When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_plic.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)