| Message ID | 035e50d6438660130233c472de56b883e369f6d4.1566603412.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V Hypervisor Extension v0.4 | expand |
On Fri, 23 Aug 2019 16:38:42 PDT (-0700), Alistair Francis wrote: > Mark both sstatus and vsstatus as dirty (3). > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/translate.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 8ac72c6470..19771904f4 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -44,6 +44,7 @@ typedef struct DisasContext { > /* pc_succ_insn points to the instruction following base.pc_next */ > target_ulong pc_succ_insn; > target_ulong priv_ver; > + bool virt_enabled; > uint32_t opcode; > uint32_t mstatus_fs; > uint32_t misa; > @@ -398,6 +399,12 @@ static void mark_fs_dirty(DisasContext *ctx) > tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); > tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); > tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); > + > + if (ctx->virt_enabled) { > + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, vsstatus)); > + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); > + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, vsstatus)); > + } > tcg_temp_free(tmp); > } > #else > @@ -742,6 +749,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; > ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; > ctx->priv_ver = env->priv_ver; > +#if !defined(CONFIG_USER_ONLY) > + ctx->virt_enabled = riscv_cpu_virt_enabled(env); > +#else > + ctx->virt_enabled = false; > +#endif > ctx->misa = env->misa; > ctx->frm = -1; /* unknown rounding mode */ > ctx->ext_ifencei = cpu->cfg.ext_ifencei; Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8ac72c6470..19771904f4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -44,6 +44,7 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; + bool virt_enabled; uint32_t opcode; uint32_t mstatus_fs; uint32_t misa; @@ -398,6 +399,12 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, vsstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, vsstatus)); + } tcg_temp_free(tmp); } #else @@ -742,6 +749,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->priv_ver = env->priv_ver; +#if !defined(CONFIG_USER_ONLY) + ctx->virt_enabled = riscv_cpu_virt_enabled(env); +#else + ctx->virt_enabled = false; +#endif ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei;
Mark both sstatus and vsstatus as dirty (3). Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/translate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)