Show patches with: Submitter = Palmer Dabbelt       |    State = Action Required       |    Archived = No       |   530 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
RISC-V: virt: This is a "sifive,test1" test finisher RISC-V: virt: This is a "sifive,test1" test finisher - 1 - - 0 0 0 2019-11-07 Palmer Dabbelt New
[PULL] MAINTAINERS: Change to my personal email address [PULL] MAINTAINERS: Change to my personal email address - - 1 - 0 0 0 2019-11-01 Palmer Dabbelt New
[PULL] Update my MAINTAINERS file entry [PULL] Update my MAINTAINERS file entry - - - - 0 0 0 2019-11-01 Palmer Dabbelt New
[PULL,18/18] target/riscv: PMP violation due to wrong size parameter [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,17/18] riscv/boot: Fix possible memory leak [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 3 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,16/18] target/riscv: Make the priv register writable by GDB [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 1 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,15/18] target/riscv: Expose "priv" register for GDB for reads [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 1 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,14/18] target/riscv: Tell gdbstub the correct number of CSRs [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,13/18] riscv/virt: Jump to pflash if specified [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 1 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,12/18] riscv/virt: Add the PFlash CFI01 device [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 1 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,11/18] riscv/virt: Manually define the machine [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 1 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,10/18] riscv/sifive_u: Add the start-in-flash property [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 1 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,09/18] riscv/sifive_u: Manually define the machine [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 1 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,08/18] riscv/sifive_u: Add QSPI memory region [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,07/18] riscv/sifive_u: Add L2-LIM cache memory [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,06/18] linux-user/riscv: Propagate fault address [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,05/18] riscv: sifive_u: Add ethernet0 to the aliases node [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,03/18] RISC-V: Implement cpu_do_transaction_failed [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,02/18] RISC-V: Handle bus errors in the page table walker [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - 0 0 0 2019-10-28 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 - - - - 0 0 0 2019-10-28 Palmer Dabbelt New
RISC-V: fcvt can set fflags, so set FS accordingly RISC-V: fcvt can set fflags, so set FS accordingly - - 1 - 0 0 0 2019-10-09 Palmer Dabbelt New
[PULL,48/48] gdbstub: riscv: fix the fflags registers [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,46/48] target/riscv: Fix mstatus dirty mask [PULL,01/48] riscv: sifive_u: Add support for loading initrd - 1 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,45/48] target/riscv: Use both register name and ABI name [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,44/48] riscv: sifive_u: Update model and compatible strings in device tree [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,42/48] riscv: sifive_u: Fix broken GEM support [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,41/48] riscv: sifive_u: Instantiate OTP memory with a serial number [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,40/48] riscv: sifive: Implement a model for SiFive FU540 OTP [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,39/48] riscv: roms: Update default bios for sifive_u machine [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,38/48] riscv: sifive_u: Change UART node name in device tree [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,37/48] riscv: sifive_u: Update UART base addresses and IRQs [PULL,01/48] riscv: sifive_u: Add support for loading initrd 1 - 2 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,35/48] riscv: sifive_u: Add PRCI block to the SoC [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,33/48] riscv: sifive: Implement PRCI model for FU540 [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,32/48] riscv: sifive_u: Update PLIC hart topology configuration string [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,30/48] riscv: sifive_u: Set the minimum number of cpus to 2 [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 2 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,28/48] riscv: hart: Extract hart realize to a separate routine [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 2 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,26/48] riscv: sifive_e: Drop sifive_mmio_emulate() [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,25/48] riscv: sifive_e: prci: Update the PRCI register block size [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 2 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [PULL,01/48] riscv: sifive_u: Add support for loading initrd 1 - 2 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 2 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,22/48] riscv: sifive_u: Remove the unnecessary include of prci header [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,18/48] riscv: hw: Change create_fdt() to return void [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 3 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,17/48] riscv: hw: Remove not needed PLIC properties in device tree [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 2 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,15/48] riscv: hw: Remove superfluous "linux, phandle" property [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion [PULL,01/48] riscv: sifive_u: Add support for loading initrd - 1 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,13/48] riscv: sifive_test: Add reset functionality [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,12/48] riscv: hmp: Add a command to show virtual memory mappings [PULL,01/48] riscv: sifive_u: Add support for loading initrd 1 - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,11/48] riscv: Resolve full path of the given bios image [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,10/48] riscv: Add a helper routine for finding firmware [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,09/48] riscv: rv32: Root page table address can be larger than 32-bit [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,08/48] target/riscv: Update the Hypervisor CSRs to v0.4 [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,07/48] target/riscv: Create function to test if FP is enabled [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 2 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,06/48] riscv: plic: Remove unused interrupt functions [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 3 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,03/48] riscv: sifive_u: Fix clock-names property for ethernet node [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart Untitled series #131345 - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL,01/48] riscv: sifive_u: Add support for loading initrd [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 - - 1 - 0 0 0 2019-09-18 Palmer Dabbelt New
vl.c: Report unknown machines correctly vl.c: Report unknown machines correctly - - 1 - 0 0 0 2019-09-15 Palmer Dabbelt New
[PULL,47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,46/47] target/riscv: Fix mstatus dirty mask [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,45/47] target/riscv: Use both register name and ABI name [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,44/47] riscv: sifive_u: Update model and compatible strings in device tree [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,42/47] riscv: sifive_u: Fix broken GEM support [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,41/47] riscv: sifive_u: Instantiate OTP memory with a serial number [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,40/47] riscv: sifive: Implement a model for SiFive FU540 OTP [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,39/47] riscv: roms: Update default bios for sifive_u machine [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,38/47] riscv: sifive_u: Change UART node name in device tree [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,37/47] riscv: sifive_u: Update UART base addresses and IRQs [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 1 - 2 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,35/47] riscv: sifive_u: Add PRCI block to the SoC [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,33/47] riscv: sifive: Implement PRCI model for FU540 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,32/47] riscv: sifive_u: Update PLIC hart topology configuration string [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,30/47] riscv: sifive_u: Set the minimum number of cpus to 2 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,28/47] riscv: hart: Extract hart realize to a separate routine [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 2 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,26/47] riscv: sifive_e: Drop sifive_mmio_emulate() [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,25/47] riscv: sifive_e: prci: Update the PRCI register block size [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 2 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 1 - 2 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 2 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,22/47] riscv: sifive_u: Remove the unnecessary include of prci header [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
[PULL,19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - 0 0 0 2019-09-10 Palmer Dabbelt New
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