[v1,18/28] target/riscv: Add hfence instructions

Message ID	d0a6c68c4af8e3f160cce19fea8bbd9f20aea0be.1566603412.git.alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: Bem2yzEK2KW99nu8hf0R7/5YcJwiUaHIskjdtZbEQNIGKXEpIrFNsA5XBUwcCfzXnXf1ZqInf6 KSwcmOSGXDxq/HOpUkqNOe5rvCAWq2ein364/ZeOihKYSi3VcGVVfu7FEASKbZp1qy4yHns9Y1 jAf4kT/PuQA2Jj4UJH3oM5mPe/+0Ef8DqryRlizdY7COfHVwhagex77Hq/UYSCY5xKcGwY1aJW DhHdeNDKmhmIKwgzmP3sieDMGkAgZZNPQ5mJaP+II5uE2cxdMmVhFIs0wqmEgLBs5iEyKH/DGd CCE= IronPort-SDR: NbnQSKNJGY636EN5RmNOWEHxHPf7sxNh1hnkhT+4Defr4MtWzAOfj3TVRVvtvr5c0SsaggoYp5 mw6H+BVoOqDwpgJIuEafZzFSZa+pdMwgwS4aY4ndfEcqrX6sYT4EzN4zECQJVhLmIr0sNbjPHO 7urtjQlW7EsayGcuauZ/L54gYR9mivfQrEBi/yaAA+EIv/v4ZebSLF0Knu7zXkE+1P85GhO4Hu rH+j5DmSM7UwS7/LrXuKYUso+PnAd70GYI5NEEPUSn6Hl//4ON3qVuL//7KKNLtqIbbWcD6YEc Bz8fcinuVlABIWpGIeNnEFKX IronPort-SDR: 9gORWUnr0Q9e5zFHcsXb9cIRT7Cl94Cuqd/Gh7bkYaw6utYO4fXT4TsLiHtseUh4oUtVlQdb0W m/0v2uzGI/nz5lMedogViKnF1AW0Mw9mDfNBeiak9sC5Jw1NUp6MG5IXLPSePeuAsqoRBIHnhV 3JOhVbqzh4TtPD608l3v40AHB0Bz3Wa6sgbySS9+cPlFislYERcA5G08EY++9GvAxN/IsIzKrc L5eF50LC5aNeH88knC8xBVlhWTEqko9H4MtMLl5a3685W/BFoODopPl4NzG2A2UT9nsRBSi1RE QZc= WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 23 Aug 2019 16:38:36 -0700 Message-Id: <d0a6c68c4af8e3f160cce19fea8bbd9f20aea0be.1566603412.git.alistair.francis@wdc.com> In-Reply-To: <cover.1566603412.git.alistair.francis@wdc.com> References: <cover.1566603412.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions Precedence: list Cc: alistair23@gmail.com, Anup.Patel@wdc.com, palmer@sifive.com, alistair.francis@wdc.com, Atish.Patra@wdc.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Add RISC-V Hypervisor Extension v0.4 \| expand [v1,00/28] Add RISC-V Hypervisor Extension v0.4 [v1,01/28] target/riscv: Add the Hypervisor extension [v1,03/28] target/riscv: Add the force HS exception mode [v1,04/28] target/riscv: Fix CSR perm checking for HS mode [v1,05/28] target/riscv: Add the Hypervisor CSRs to CPUState [v1,06/28] target/riscv: Print priv and virt in disas log [v1,07/28] target/riscv: Dump Hypervisor registers if enabled [v1,08/28] target/riscv: Add Hypervisor CSR access functions [v1,09/28] target/riscv: Add Hypervisor virtual CSRs accesses [v1,10/28] target/riscv: Convert mie and mstatus to pointers [v1,11/28] target/riscv: Add background register swapping function [v1,12/28] target/riscv: Add support for virtual interrupt setting [v1,13/28] target/ricsv: Flush the TLB on virtulisation mode changes [v1,14/28] target/riscv: Generate illegal instruction on WFI when V=1 [v1,15/28] riscv: plic: Always set sip.SEIP bit for HS [v1,16/28] target/riscv: Add hypvervisor trap support [v1,17/28] target/riscv: Add Hypervisor trap return support [v1,18/28] target/riscv: Add hfence instructions [v1,19/28] target/riscv: Disable guest FP support based on virtual status [v1,20/28] target/riscv: Mark both sstatus and vsstatus as dirty [v1,21/28] target/riscv: Respect MPRV and SPRV for floating point ops [v1,22/28] target/riscv: Allow specifying MMU stage [v1,23/28] target/riscv: Allow specifying number of MMU stages [v1,24/28] target/riscv: Implement second stage MMU [v1,25/28] target/riscv: Call the second stage MMU in virtualisation mode [v1,26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR [v1,27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [v1,28/28] target/riscv: Allow enabling the Hypervisor extension

Message ID

d0a6c68c4af8e3f160cce19fea8bbd9f20aea0be.1566603412.git.alistair.francis@wdc.com

State

New

Headers

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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Date: Fri, 23 Aug 2019 16:38:36 -0700
Message-Id: <d0a6c68c4af8e3f160cce19fea8bbd9f20aea0be.1566603412.git.alistair.francis@wdc.com>
In-Reply-To: <cover.1566603412.git.alistair.francis@wdc.com>
References: <cover.1566603412.git.alistair.francis@wdc.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions
Precedence: list
Cc: alistair23@gmail.com, Anup.Patel@wdc.com, palmer@sifive.com,
	alistair.francis@wdc.com, Atish.Patra@wdc.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

Add RISC-V Hypervisor Extension v0.4 | expand

Commit Message

Alistair Francis Aug. 23, 2019, 11:38 p.m. UTC

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode                    | 23 ++++++-----
 .../riscv/insn_trans/trans_privileged.inc.c   | 40 +++++++++++++++++++
 2 files changed, 54 insertions(+), 9 deletions(-)

Comments

Palmer Dabbelt Oct. 1, 2019, 6:34 p.m. UTC | #1

On Fri, 23 Aug 2019 16:38:36 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/insn32.decode                    | 23 ++++++-----
>  .../riscv/insn_trans/trans_privileged.inc.c   | 40 +++++++++++++++++++
>  2 files changed, 54 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 77f794ed70..cfd9ca6d2b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -63,20 +63,25 @@
>  @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
>  @r2      .......   ..... ..... ... ..... ....... %rs1 %rd
>
> +@hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
> +@hfence_bvma ....... ..... .....   ... ..... ....... %rs2 %rs1
> +
>  @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
>  @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
>
>
>  # *** Privileged Instructions ***
> -ecall      000000000000     00000 000 00000 1110011
> -ebreak     000000000001     00000 000 00000 1110011
> -uret       0000000    00010 00000 000 00000 1110011
> -sret       0001000    00010 00000 000 00000 1110011
> -hret       0010000    00010 00000 000 00000 1110011
> -mret       0011000    00010 00000 000 00000 1110011
> -wfi        0001000    00101 00000 000 00000 1110011
> -sfence_vma 0001001    ..... ..... 000 00000 1110011 @sfence_vma
> -sfence_vm  0001000    00100 ..... 000 00000 1110011 @sfence_vm
> +ecall       000000000000     00000 000 00000 1110011
> +ebreak      000000000001     00000 000 00000 1110011
> +uret        0000000    00010 00000 000 00000 1110011
> +sret        0001000    00010 00000 000 00000 1110011
> +hret        0010000    00010 00000 000 00000 1110011
> +mret        0011000    00010 00000 000 00000 1110011
> +wfi         0001000    00101 00000 000 00000 1110011
> +hfence_gvma 0110001    ..... ..... 000 00000 1110011 @hfence_gvma
> +hfence_bvma 0010001    ..... ..... 000 00000 1110011 @hfence_bvma
> +sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
> +sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm
>
>  # *** RV32I Base Instruction Set ***
>  lui      ....................       ..... 0110111 @u
> diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
> index c5e4b3e49a..b9b5a89b52 100644
> --- a/target/riscv/insn_trans/trans_privileged.inc.c
> +++ b/target/riscv/insn_trans/trans_privileged.inc.c
> @@ -108,3 +108,43 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
>  #endif
>      return false;
>  }
> +
> +static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> +    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
> +        has_ext(ctx, RVH)) {
> +        /* Hpervisor extensions exist */
> +        /*
> +         * if (env->priv == PRV_M ||
> +         *   (env->priv == PRV_S &&
> +         *    !riscv_cpu_virt_enabled(env) &&
> +         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
> +         */
> +            gen_helper_tlb_flush(cpu_env);
> +            return true;
> +        /* } */
> +    }
> +#endif
> +    return false;
> +}
> +
> +static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> +    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
> +        has_ext(ctx, RVH)) {
> +        /* Hpervisor extensions exist */
> +        /*
> +         * if (env->priv == PRV_M ||
> +         *   (env->priv == PRV_S &&
> +         *    !riscv_cpu_virt_enabled(env) &&
> +         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
> +         */
> +            gen_helper_tlb_flush(cpu_env);
> +            return true;
> +        /* } */
> +    }
> +#endif
> +    return false;
> +}

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 77f794ed70..cfd9ca6d2b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -63,20 +63,25 @@ 
 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
 @r2      .......   ..... ..... ... ..... ....... %rs1 %rd
 
+@hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
+@hfence_bvma ....... ..... .....   ... ..... ....... %rs2 %rs1
+
 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
 
 
 # *** Privileged Instructions ***
-ecall      000000000000     00000 000 00000 1110011
-ebreak     000000000001     00000 000 00000 1110011
-uret       0000000    00010 00000 000 00000 1110011
-sret       0001000    00010 00000 000 00000 1110011
-hret       0010000    00010 00000 000 00000 1110011
-mret       0011000    00010 00000 000 00000 1110011
-wfi        0001000    00101 00000 000 00000 1110011
-sfence_vma 0001001    ..... ..... 000 00000 1110011 @sfence_vma
-sfence_vm  0001000    00100 ..... 000 00000 1110011 @sfence_vm
+ecall       000000000000     00000 000 00000 1110011
+ebreak      000000000001     00000 000 00000 1110011
+uret        0000000    00010 00000 000 00000 1110011
+sret        0001000    00010 00000 000 00000 1110011
+hret        0010000    00010 00000 000 00000 1110011
+mret        0011000    00010 00000 000 00000 1110011
+wfi         0001000    00101 00000 000 00000 1110011
+hfence_gvma 0110001    ..... ..... 000 00000 1110011 @hfence_gvma
+hfence_bvma 0010001    ..... ..... 000 00000 1110011 @hfence_bvma
+sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
+sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm
 
 # *** RV32I Base Instruction Set ***
 lui      ....................       ..... 0110111 @u
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
index c5e4b3e49a..b9b5a89b52 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -108,3 +108,43 @@  static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
 #endif
     return false;
 }
+
+static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+        has_ext(ctx, RVH)) {
+        /* Hpervisor extensions exist */
+        /*
+         * if (env->priv == PRV_M ||
+         *   (env->priv == PRV_S &&
+         *    !riscv_cpu_virt_enabled(env) &&
+         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+         */
+            gen_helper_tlb_flush(cpu_env);
+            return true;
+        /* } */
+    }
+#endif
+    return false;
+}
+
+static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+        has_ext(ctx, RVH)) {
+        /* Hpervisor extensions exist */
+        /*
+         * if (env->priv == PRV_M ||
+         *   (env->priv == PRV_S &&
+         *    !riscv_cpu_virt_enabled(env) &&
+         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+         */
+            gen_helper_tlb_flush(cpu_env);
+            return true;
+        /* } */
+    }
+#endif
+    return false;
+}

[v1,18/28] target/riscv: Add hfence instructions

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Patch