Show patches with: Archived = No       |   167497 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v3,7/7] riscv: Enable watchdog for the k210 wdt: Add support for watchdogs on Kendryte K210 - - 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,6/7] riscv: Add watchdog bindings for the k210 wdt: Add support for watchdogs on Kendryte K210 1 - - - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,5/7] wdt: dw: Free the clock on error wdt: Add support for watchdogs on Kendryte K210 - - 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,4/7] wdt: dw: Enable the clock before using it wdt: Add support for watchdogs on Kendryte K210 - 1 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,3/7] wdt: dw: Fix clock rate being off by 1000 wdt: Add support for watchdogs on Kendryte K210 - 1 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,2/7] wdt: dw: Switch to if(CONFIG()) instead of using #if wdt: Add support for watchdogs on Kendryte K210 - - 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,1/7] wdt: dw: Switch to using fls for log2 wdt: Add support for watchdogs on Kendryte K210 - - 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,7/7] riscv: Update SiFive device tree for new CLINT driver riscv: Clean up timer drivers - - 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,6/7] riscv: Update Kendryte device tree for new CLINT driver riscv: Clean up timer drivers - - - - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,5/7] riscv: clk: Add CLINT clock to kendryte clock driver riscv: Clean up timer drivers - - - - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,4/7] riscv: Rework Sifive CLINT as UCLASS_TIMER driver riscv: Clean up timer drivers - - 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,3/7] riscv: Clean up initialization in Andes PLIC riscv: Clean up timer drivers - - - - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,2/7] riscv: Rework Andes PLMT as a UCLASS_TIMER driver riscv: Clean up timer drivers - - 1 - --- 2020-09-01 Sean Anderson Andes Superseded
[v3,1/7] riscv: Rework riscv timer driver to only support S-mode riscv: Clean up timer drivers - - 2 - --- 2020-09-01 Sean Anderson Andes Superseded
cmd: irq: disable CMD_IRQ for riscv arch cmd: irq: disable CMD_IRQ for riscv arch - - 3 - --- 2020-08-24 Pragnesh Patel Andes Accepted
[3/3] riscv: Mark andes_plmt_get_count() with 'notrace' RISC-V tracing support - - - - --- 2020-08-24 Pragnesh Patel Andes Superseded
[2/3] riscv: Mark riscv_timer_get_count() and sifive_clint_get_count() with 'notrace' RISC-V tracing support - - - - --- 2020-08-24 Pragnesh Patel Andes Superseded
[1/3] riscv: Add timer_get_us() for tracing RISC-V tracing support - - - - --- 2020-08-24 Pragnesh Patel Andes Superseded
riscv: Add do_irqinfo() for CONFIG_CMD_IRQ riscv: Add do_irqinfo() for CONFIG_CMD_IRQ - - - - --- 2020-08-24 Pragnesh Patel Andes Changes Requested
[v5,1/1] cmd: provide command sbi [v5,1/1] cmd: provide command sbi - - 4 3 --- 2020-08-20 Heinrich Schuchardt Andes Accepted
[v3,1/1] cmd: provide command sbi [v3,1/1] cmd: provide command sbi - - 2 1 --- 2020-08-19 Heinrich Schuchardt Andes Superseded
[v2,1/1] cmd: provide command sbi [v2,1/1] cmd: provide command sbi - - - - --- 2020-08-18 Heinrich Schuchardt Andes Superseded
[2/2] ram: sifive: Fix compiler warnings for 32-bit [1/2] riscv: fu540: Use correct API to get L2 cache controller base address - - 2 - --- 2020-08-18 Bin Meng Andes Accepted
[1/2] riscv: fu540: Use correct API to get L2 cache controller base address [1/2] riscv: fu540: Use correct API to get L2 cache controller base address - - 2 - --- 2020-08-18 Bin Meng Andes Accepted
[v2,1/1] configs: defconfig for Sipeed Maix in S-mode [v2,1/1] configs: defconfig for Sipeed Maix in S-mode - - 2 - --- 2020-08-17 Heinrich Schuchardt Andes Accepted
[v2,1/1] riscv: fix building with CONFIG_SPL_SMP=n [v2,1/1] riscv: fix building with CONFIG_SPL_SMP=n - 2 4 - --- 2020-08-15 Heinrich Schuchardt Andes Accepted
[1/1] riscv: don't jump to 0x0 in handle_ipi() [1/1] riscv: don't jump to 0x0 in handle_ipi() - - - - --- 2020-08-11 Heinrich Schuchardt Andes Rejected
[v2,7/7] riscv: Enable watchdog for the k210 [v2,1/7] wdt: dw: Switch to using fls for log2 - - - - --- 2020-08-07 Sean Anderson Andes Superseded
[v2,6/7] riscv: Add watchdog bindings for the k210 [v2,1/7] wdt: dw: Switch to using fls for log2 1 - - - --- 2020-08-07 Sean Anderson Andes Superseded
[v2,10/10] riscv: Add support for SPI on Kendryte K210 riscv: Add SPI support for Kendryte K210 - - - - --- 2020-08-07 Sean Anderson Andes Superseded
[v2,09/10] riscv: Add device tree bindings for SPI riscv: Add SPI support for Kendryte K210 1 - - - --- 2020-08-07 Sean Anderson Andes Superseded
[3/3] spi: Fix typo in header Misc fixes/cleanup - - - - --- 2020-08-07 Sean Anderson Andes Superseded
[2/3] spi: Remove uses of #ifdef __U_BOOT__ from spi-mem.c Misc fixes/cleanup - - - - --- 2020-08-07 Sean Anderson Andes Superseded
[1/3] doc: Fix typo in FIT documentation Misc fixes/cleanup - - 1 - --- 2020-08-07 Sean Anderson Andes Superseded
[7/7] riscv: Enable watchdog for the k210 [1/7] wdt: dw: Switch to using fls for log2 - - - - --- 2020-08-05 Sean Anderson Andes Superseded
[6/7] riscv: Add watchdog bindings for the k210 [1/7] wdt: dw: Switch to using fls for log2 - - - - --- 2020-08-05 Sean Anderson Andes Superseded
[5/7] wdt: dw: Free the clock on error [1/7] wdt: dw: Switch to using fls for log2 - - 1 - --- 2020-08-05 Sean Anderson Andes Superseded
[4/7] wdt: dw: Enable the clock before using it [1/7] wdt: dw: Switch to using fls for log2 - 1 1 - --- 2020-08-05 Sean Anderson Andes Superseded
[3/7] wdt: dw: Fix clock rate being off by 1000 [1/7] wdt: dw: Switch to using fls for log2 - 1 1 - --- 2020-08-05 Sean Anderson Andes Superseded
[2/7] wdt: dw: Switch to if(CONFIG()) instead of using #if [1/7] wdt: dw: Switch to using fls for log2 - - 1 - --- 2020-08-05 Sean Anderson Andes Superseded
[1/7] wdt: dw: Switch to using fls for log2 [1/7] wdt: dw: Switch to using fls for log2 - - - - --- 2020-08-05 Sean Anderson Andes Superseded
riscv: Remove unused define in maix header riscv: Remove unused define in maix header - - 2 - --- 2020-08-05 Sean Anderson Andes Superseded
[6/6] riscv: sifive/fu540: Move SPL related functions to spl.c [1/6] riscv: Call spl_board_init_f() in the generic SPL board_init_f() - - 3 1 --- 2020-08-03 Bin Meng Andes Accepted
[5/6] riscv: sifive/fu540: Drop NET_RANDOM_ETHADDR [1/6] riscv: Call spl_board_init_f() in the generic SPL board_init_f() - - 3 1 --- 2020-08-03 Bin Meng Andes Accepted
[4/6] riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level [1/6] riscv: Call spl_board_init_f() in the generic SPL board_init_f() - - 2 1 --- 2020-08-03 Bin Meng Andes Accepted
[3/6] riscv: sifive/fu540: spl: Rename soc_spl_init() [1/6] riscv: Call spl_board_init_f() in the generic SPL board_init_f() - - 2 1 --- 2020-08-03 Bin Meng Andes Accepted
[2/6] riscv: sifive/fu540: spl: Drop our own version of board_init_f() [1/6] riscv: Call spl_board_init_f() in the generic SPL board_init_f() - - 2 1 --- 2020-08-03 Bin Meng Andes Accepted
[1/6] riscv: Call spl_board_init_f() in the generic SPL board_init_f() [1/6] riscv: Call spl_board_init_f() in the generic SPL board_init_f() - - 2 1 --- 2020-08-03 Bin Meng Andes Accepted
[v2,1/1] riscv: additional crash information [v2,1/1] riscv: additional crash information - - 1 1 --- 2020-08-01 Heinrich Schuchardt Andes Superseded
[v2,7/7] riscv: Update SiFive device tree for new CLINT driver riscv: Clean up timer drivers - - - - --- 2020-07-29 Sean Anderson Andes Superseded
[v2,6/7] riscv: Update Kendryte device tree for new CLINT driver riscv: Clean up timer drivers - - - - --- 2020-07-29 Sean Anderson Andes Superseded
[v2,5/7] riscv: clk: Add CLINT clock to kendryte clock driver riscv: Clean up timer drivers - - - - --- 2020-07-29 Sean Anderson Andes Superseded
[v2,4/7] riscv: Rework Sifive CLINT as UCLASS_TIMER driver riscv: Clean up timer drivers - - - - --- 2020-07-29 Sean Anderson Andes Superseded
[v2,3/7] riscv: Clean up initialization in Andes PLIC riscv: Clean up timer drivers - - 1 - --- 2020-07-29 Sean Anderson Andes Superseded
[v2,2/7] riscv: Rework Andes PLMT as a UCLASS_TIMER driver riscv: Clean up timer drivers - - - - --- 2020-07-29 Sean Anderson Andes Superseded
[v2,1/7] riscv: Rework riscv timer driver to only support S-mode riscv: Clean up timer drivers - - 1 - --- 2020-07-29 Sean Anderson Andes Superseded
[v5,5/5] configs: reset: fu540: enable dm reset framework for SiFive add DM based reset driver for SiFive SoC's - - 2 1 --- 2020-07-29 Sagar Shrikant Kadam Andes Accepted
[v5,4/5] sifive: reset: add DM based reset driver for SiFive SoC's add DM based reset driver for SiFive SoC's - - 2 1 --- 2020-07-29 Sagar Shrikant Kadam Andes Accepted
[v5,3/5] fu540: dtsi: add reset producer and consumer entries add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-29 Sagar Shrikant Kadam Andes Accepted
[v5,2/5] fu540: prci: use common reset indexes defined in binding header add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-29 Sagar Shrikant Kadam Andes Accepted
[v5,1/5] dt-bindings: prci: add indexes for reset signals available in prci add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-29 Sagar Shrikant Kadam Andes Accepted
[1/1] clk: kendryte/pll.h: do not redefine nop() [1/1] clk: kendryte/pll.h: do not redefine nop() - - 2 - --- 2020-07-28 Heinrich Schuchardt Andes Accepted
[v4,5/5] configs: reset: fu540: enable dm reset framework for SiFive add DM based reset driver for SiFive SoC's - - 2 1 --- 2020-07-24 Sagar Shrikant Kadam Andes Superseded
[v4,4/5] sifive: reset: add DM based reset driver for SiFive SoC's add DM based reset driver for SiFive SoC's - - 2 1 --- 2020-07-24 Sagar Shrikant Kadam Andes Superseded
[v4,3/5] fu540: dtsi: add reset producer and consumer entries Untitled series #192028 - - 2 - --- 2020-07-24 Sagar Shrikant Kadam Andes Superseded
[v4,3/5] fu540: dtsi: add reset producer and consumer entries add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-24 Sagar Shrikant Kadam Andes Superseded
[v4,2/5] fu540: prci: use common reset indexes defined in binding header add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-24 Sagar Shrikant Kadam Andes Superseded
[v4,1/5] dt-bindings: prci: add indexes for reset signals available in prci add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-24 Sagar Shrikant Kadam Andes Superseded
[6/6] riscv: Update SiFive device tree for new CLINT driver riscv: Clean up timer drivers - - - - --- 2020-07-22 Sean Anderson Andes Superseded
[5/6] riscv: Update Kendryte device tree for new CLINT driver riscv: Clean up timer drivers - - - - --- 2020-07-22 Sean Anderson Andes Superseded
[4/6] riscv: Rework Sifive CLINT as UCLASS_TIMER driver riscv: Clean up timer drivers - - - - --- 2020-07-22 Sean Anderson Andes Superseded
[3/6] riscv: Clean up initialization in Andes PLIC riscv: Clean up timer drivers - - - - --- 2020-07-22 Sean Anderson Andes Superseded
[2/6] riscv: Rework Andes PLMT as a UCLASS_TIMER driver riscv: Clean up timer drivers - - - - --- 2020-07-22 Sean Anderson Andes Superseded
[1/6] riscv: Rework riscv timer driver to only support S-mode riscv: Clean up timer drivers - - - - --- 2020-07-22 Sean Anderson Andes Superseded
[v4] riscv: Make SiFive HiFive Unleashed board boot again [v4] riscv: Make SiFive HiFive Unleashed board boot again - 1 1 1 --- 2020-07-20 Bin Meng Andes Accepted
[v2,2/2] ram: sifive: Avoid using hardcoded ram base and size [v2,1/2] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL - - 2 - --- 2020-07-20 Bin Meng Andes Accepted
[v2,1/2] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL [v2,1/2] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL - - 1 - --- 2020-07-20 Bin Meng Andes Accepted
[RESEND,v3] riscv: Make SiFive HiFive Unleashed board boot again [RESEND,v3] riscv: Make SiFive HiFive Unleashed board boot again - 1 - - --- 2020-07-20 Bin Meng Andes Superseded
[v3] azure: gitlab: travis: Update OpenSBI used for RISC-V testing [v3] azure: gitlab: travis: Update OpenSBI used for RISC-V testing - - 1 - --- 2020-07-20 Bin Meng Andes Accepted
[v2,2/2] Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"" [v2,1/2] Revert "riscv: Allow use of reset drivers" - - - - --- 2020-07-20 Bin Meng Andes Accepted
[v2,1/2] Revert "riscv: Allow use of reset drivers" [v2,1/2] Revert "riscv: Allow use of reset drivers" - - 2 - --- 2020-07-20 Bin Meng Andes Accepted
riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc reg riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc reg 1 - 1 1 --- 2020-07-17 Andes Andes Accepted
[v2] azure: gitlab: travis: Update OpenSBI used for RISC-V testing [v2] azure: gitlab: travis: Update OpenSBI used for RISC-V testing - - 1 - --- 2020-07-16 Bin Meng Andes Superseded
[4/4] ram: sifive: Avoid using hardcoded ram base and size [1/4] fdtdec: Add fdtdec_get_mem_size_base() - - - - --- 2020-07-16 Bin Meng Andes Superseded
[3/4] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL [1/4] fdtdec: Add fdtdec_get_mem_size_base() - - - - --- 2020-07-16 Bin Meng Andes Superseded
[2/4] fdtdec: Update fdtdec_setup_mem_size_base_fdt() to call fdtdec_get_mem_size_base() [1/4] fdtdec: Add fdtdec_get_mem_size_base() - - - - --- 2020-07-16 Bin Meng Andes Superseded
[1/4] fdtdec: Add fdtdec_get_mem_size_base() [1/4] fdtdec: Add fdtdec_get_mem_size_base() - - - - --- 2020-07-16 Bin Meng Andes Superseded
[v5,6/6] sifive: fu540: Enable SF distro bootcmd riscv: sifive/fu540: SPI boot - - 1 - --- 2020-07-15 Jagan Teki Andes Accepted
[v5,5/6] sifive: fu540: Add boot flash script offset, size riscv: sifive/fu540: SPI boot - - 1 - --- 2020-07-15 Jagan Teki Andes Accepted
[v5,4/6] sifive: fu540: Mark the default env as SPI flash riscv: sifive/fu540: SPI boot - - 2 1 --- 2020-07-15 Jagan Teki Andes Accepted
[v5,3/6] env: Enable SPI flash env for SiFive FU540 riscv: sifive/fu540: SPI boot - - 1 1 --- 2020-07-15 Jagan Teki Andes Accepted
[v5,2/6] sifive: fu540: Add Booting from SPI riscv: sifive/fu540: SPI boot - - 1 1 --- 2020-07-15 Jagan Teki Andes Accepted
[v5,1/6] sifive: fu540: Add runtime boot mode detection riscv: sifive/fu540: SPI boot - - 1 1 --- 2020-07-15 Jagan Teki Andes Accepted
[v2] serial: Fix SIFIVE debug serial dependency [v2] serial: Fix SIFIVE debug serial dependency - 1 4 - --- 2020-07-10 Michal Simek Andes Accepted
[v3,5/5] configs: reset: fu540: enable dm reset framework for SiFive SoC add DM based reset driver for SiFive SoC's - - 2 1 --- 2020-07-10 Sagar Shrikant Kadam Andes Superseded
[v3,4/5] sifive: reset: add DM based reset driver for SiFive SoC's add DM based reset driver for SiFive SoC's - - 2 1 --- 2020-07-10 Sagar Shrikant Kadam Andes Superseded
[v3,3/5] fu540: dtsi: add reset producer and consumer entries add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-10 Sagar Shrikant Kadam Andes Superseded
[v3,2/5] fu540: prci: use common reset indexes defined in binding header add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-10 Sagar Shrikant Kadam Andes Superseded
[v3,1/5] dt-bindings: prci: add indexes for reset signals available in prci add DM based reset driver for SiFive SoC's - - 2 - --- 2020-07-10 Sagar Shrikant Kadam Andes Superseded
[2/2] Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"" [1/2] Revert "riscv: Allow use of reset drivers" - - - - --- 2020-07-08 Bin Meng Andes Accepted
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