diff mbox series

[v2,1/1] riscv: fix building with CONFIG_SPL_SMP=n

Message ID 20200815074926.11692-1-xypron.glpk@gmx.de
State Accepted
Commit 092f15aee5bdebc010ad99120bab96162d9c64c8
Delegated to: Andes
Headers show
Series [v2,1/1] riscv: fix building with CONFIG_SPL_SMP=n | expand

Commit Message

Heinrich Schuchardt Aug. 15, 2020, 7:49 a.m. UTC
Building with CONFIG_SPL_SMP=n results in:

arch/riscv/lib/spl.c: In function ‘jump_to_image_no_args’:
arch/riscv/lib/spl.c:33:6:
error: unused variable ‘ret’ [-Werror=unused-variable]
   33 |  int ret;
      |      ^~~

Define the variable ret as __maybe_unused.

Fixes: 191636e44898 ("riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL")
Fixes: 8c59f2023cc8 ("riscv: add SPL support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
---
v2:
	Do not break Fixes line
---
 arch/riscv/lib/spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
2.27.0

Comments

Pragnesh Patel Aug. 20, 2020, 12:32 p.m. UTC | #1
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Heinrich Schuchardt
>Sent: 15 August 2020 13:19
>To: Rick Chen <rick@andestech.com>
>Cc: Simon Glass <sjg@chromium.org>; Bin Meng <bin.meng@windriver.com>;
>Anup Patel <anup.patel@wdc.com>; Lukas Auer
><lukas.auer@aisec.fraunhofer.de>; u-boot@lists.denx.de; Heinrich Schuchardt
><xypron.glpk@gmx.de>
>Subject: [PATCH v2 1/1] riscv: fix building with CONFIG_SPL_SMP=n
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Building with CONFIG_SPL_SMP=n results in:
>
>arch/riscv/lib/spl.c: In function ‘jump_to_image_no_args’:
>arch/riscv/lib/spl.c:33:6:
>error: unused variable ‘ret’ [-Werror=unused-variable]
>   33 |  int ret;
>      |      ^~~
>
>Define the variable ret as __maybe_unused.
>
>Fixes: 191636e44898 ("riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL")
>Fixes: 8c59f2023cc8 ("riscv: add SPL support")
>Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
>Reviewed-by: Bin Meng <bin.meng@windriver.com>
>Reviewed-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Rick Chen <rick@andestech.com>
>---
>v2:
>        Do not break Fixes line
>---
> arch/riscv/lib/spl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
diff mbox series

Patch

diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
index c47dcd46ce..ef00ec2bcc 100644
--- a/arch/riscv/lib/spl.c
+++ b/arch/riscv/lib/spl.c
@@ -30,7 +30,7 @@  void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
 	typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb);
 	void *fdt_blob;
-	int ret;
+	__maybe_unused int ret;

 #if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
 	fdt_blob = spl_image->fdt_addr;