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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
RISC-V/testsuite: Fix pr105666.c under rv32
RISC-V/testsuite: Fix pr105666.c under rv32
- - - -
-
-
-
2022-06-08
Jiawei
New
RISC-V/testsuite: Fix zvfh tests.
RISC-V/testsuite: Fix zvfh tests.
- - - -
-
-
-
2023-11-09
Robin Dapp
New
RISC-V/testsuite: Restrict remaining `fmin'/`fmax' tests to hard float
RISC-V/testsuite: Restrict remaining `fmin'/`fmax' tests to hard float
- - - -
-
-
-
2022-07-28
Maciej W. Rozycki
New
RISC-V/testsuite: Run target testing over all the usual optimization levels
RISC-V/testsuite: Run target testing over all the usual optimization levels
- - - -
-
-
-
2022-01-31
Maciej W. Rozycki
New
RISC-V/testsuite: add a default march (lacking zfa) to some fp tests
RISC-V/testsuite: add a default march (lacking zfa) to some fp tests
- - - -
-
-
-
2023-10-15
Vineet Gupta
New
RISC-V/testsuite: constraint some of tests to hard_float
RISC-V/testsuite: constraint some of tests to hard_float
- - - -
-
-
-
2022-05-27
Vineet Gupta
New
RISC-V: 'Zfa' extension is now ratified
RISC-V: 'Zfa' extension is now ratified
- - - -
-
-
-
2023-10-21
Tsukasa OI
New
RISC-V: ADJUST_NUNITS according to -march.
RISC-V: ADJUST_NUNITS according to -march.
- - - -
-
-
-
2022-10-25
juzhe.zhong@rivai.ai
New
RISC-V: Adapt live-1.c testcase
RISC-V: Adapt live-1.c testcase
- - - -
-
-
-
2023-08-23
juzhe.zhong@rivai.ai
New
RISC-V: Add "m_" prefix for private member
RISC-V: Add "m_" prefix for private member
- - - -
-
-
-
2023-05-22
juzhe.zhong@rivai.ai
New
RISC-V: Add (u)int8_t to binop tests.
RISC-V: Add (u)int8_t to binop tests.
- - - -
-
-
-
2023-06-14
Robin Dapp
New
RISC-V: Add --specs=nosys.specs support.
RISC-V: Add --specs=nosys.specs support.
- - - -
-
-
-
2018-01-26
Jim Wilson
New
RISC-V: Add --with-cmodel configure-time argument
RISC-V: Add --with-cmodel configure-time argument
- - - -
-
-
-
2023-12-20
Palmer Dabbelt
New
RISC-V: Add -X to link spec
RISC-V: Add -X to link spec
- - - -
-
-
-
2024-04-23
Fangrui Song
New
RISC-V: Add -fno-vect-cost-model to pr112773 testcase
RISC-V: Add -fno-vect-cost-model to pr112773 testcase
- - - -
-
-
-
2023-12-14
Patrick O'Neill
New
RISC-V: Add -malign-data= option.
RISC-V: Add -malign-data= option.
- - - -
-
-
-
2019-06-25
Ilia Diachkov
New
RISC-V: Add -mpreferred-stack-boundary option.
RISC-V: Add -mpreferred-stack-boundary option.
- - - -
-
-
-
2018-01-23
Jim Wilson
New
RISC-V: Add -mstrict-align option
- - - -
-
-
-
2017-05-04
Palmer Dabbelt
New
RISC-V: Add -mstrict-align option
- - - -
-
-
-
2017-05-01
Palmer Dabbelt
New
RISC-V: Add -mtune=thead-c906 to the invoke docs
RISC-V: Add -mtune=thead-c906 to the invoke docs
- - - -
-
-
-
2022-05-26
Palmer Dabbelt
New
RISC-V: Add :: for static function calling to avoid confusing
RISC-V: Add :: for static function calling to avoid confusing
- - - -
-
-
-
2023-01-18
juzhe.zhong@rivai.ai
New
RISC-V: Add ABI requirement for XTheadFMemIdx tests
RISC-V: Add ABI requirement for XTheadFMemIdx tests
- - - -
-
-
-
2023-11-06
Christoph Müllner
New
RISC-V: Add ABI-defined RVV types.
RISC-V: Add ABI-defined RVV types.
- - - -
-
-
-
2022-09-27
juzhe.zhong@rivai.ai
New
RISC-V: Add AVL propagation PASS for RVV auto-vectorization
RISC-V: Add AVL propagation PASS for RVV auto-vectorization
- - - -
-
-
-
2023-10-24
juzhe.zhong@rivai.ai
New
RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases
RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases
- - - -
-
-
-
2023-08-16
juzhe.zhong@rivai.ai
New
RISC-V: Add FNMS floating-point VLS tests
RISC-V: Add FNMS floating-point VLS tests
- - - -
-
-
-
2023-09-19
juzhe.zhong@rivai.ai
New
RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions
RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions
- - - -
-
-
-
2023-05-15
juzhe.zhong@rivai.ai
New
RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions
RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions
- - - -
-
-
-
2023-05-15
juzhe.zhong@rivai.ai
New
RISC-V: Add FRM_ prefix to dynamic rounding mode enum
RISC-V: Add FRM_ prefix to dynamic rounding mode enum
- - - -
-
-
-
2023-05-24
juzhe.zhong@rivai.ai
New
RISC-V: Add Full 'v' extension predicate to vsmul intrinsic
RISC-V: Add Full 'v' extension predicate to vsmul intrinsic
- - - -
-
-
-
2023-02-10
juzhe.zhong@rivai.ai
New
RISC-V: Add Jim Wilson as a maintainer
RISC-V: Add Jim Wilson as a maintainer
- - - -
-
-
-
2017-11-07
Palmer Dabbelt
New
RISC-V: Add LCM delete block predecessors dump information
RISC-V: Add LCM delete block predecessors dump information
- - - -
-
-
-
2024-01-25
juzhe.zhong@rivai.ai
New
RISC-V: Add MASK vec_duplicate pattern[PR110962]
RISC-V: Add MASK vec_duplicate pattern[PR110962]
- - - -
-
-
-
2023-08-10
juzhe.zhong@rivai.ai
New
RISC-V: Add RISC-V into vect_cmdline_needed
RISC-V: Add RISC-V into vect_cmdline_needed
- - - -
-
-
-
2023-11-07
juzhe.zhong@rivai.ai
New
RISC-V: Add RTX costs for `if_then_else' expressions
RISC-V: Add RTX costs for `if_then_else' expressions
- - - -
-
-
-
2022-07-18
Maciej W. Rozycki
New
RISC-V: Add RV32E support.
RISC-V: Add RV32E support.
- - - -
-
-
-
2018-05-18
Jim Wilson
New
RISC-V: Add RVV FMA auto-vectorization support
RISC-V: Add RVV FMA auto-vectorization support
- - - -
-
-
-
2023-05-26
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV FNMA auto-vectorization support
RISC-V: Add RVV FNMA auto-vectorization support
- - - -
-
-
-
2023-05-29
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs
RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs
- - - -
-
-
-
2023-05-25
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV all mask C/C++ intrinsics support
RISC-V: Add RVV all mask C/C++ intrinsics support
- - - -
-
-
-
2023-02-16
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV auto-vectorization compile option
RISC-V: Add RVV auto-vectorization compile option
- - - -
-
-
-
2023-04-07
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV auto-vectorization testcase
RISC-V: Add RVV auto-vectorization testcase
- - - -
-
-
-
2023-04-06
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV builtin vectorization cost model
RISC-V: Add RVV builtin vectorization cost model
- - - -
-
-
-
2023-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV comparison autovectorization
RISC-V: Add RVV comparison autovectorization
- - - -
-
-
-
2023-05-20
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV constraints.
RISC-V: Add RVV constraints.
- - - -
-
-
-
2022-08-30
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV instructions classification
RISC-V: Add RVV instructions classification
- - - -
-
-
-
2022-08-27
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV intrinsic basic framework.
RISC-V: Add RVV intrinsic basic framework.
- - - -
-
-
-
2022-10-17
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV machine modes.
RISC-V: Add RVV machine modes.
- - - -
-
-
-
2022-09-15
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV machine modes.
RISC-V: Add RVV machine modes.
- - - -
-
-
-
2022-09-15
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV mask logic auto-vectorization
RISC-V: Add RVV mask logic auto-vectorization
- - - -
-
-
-
2023-05-24
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV misc intrinsic support
RISC-V: Add RVV misc intrinsic support
- - - -
-
-
-
2023-03-02
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV narrow shift right lowering auto-vectorization
RISC-V: Add RVV narrow shift right lowering auto-vectorization
- - - -
-
-
-
2023-06-12
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV reduction C/C++ intrinsics support
RISC-V: Add RVV reduction C/C++ intrinsics support
- - - -
-
-
-
2023-02-20
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV registers
RISC-V: Add RVV registers
- - - -
-
-
-
2022-08-27
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE
RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE
- - - -
-
-
-
2022-08-30
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV registers register spilling
RISC-V: Add RVV registers register spilling
- - - -
-
-
-
2022-11-06
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV shift.vx C/C++ API support
RISC-V: Add RVV shift.vx C/C++ API support
- - - -
-
-
-
2023-01-31
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.
- - - -
-
-
-
2022-10-17
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization
RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization
- - - -
-
-
-
2023-06-06
juzhe.zhong@rivai.ai
New
RISC-V: Add Sign/Zero extend patterns for PIC loads
RISC-V: Add Sign/Zero extend patterns for PIC loads
- - - -
-
-
-
2017-10-24
Palmer Dabbelt
New
RISC-V: Add Sign/Zero extend patterns for PIC loads
- - - -
-
-
-
2017-05-09
Palmer Dabbelt
New
RISC-V: Add TAREGT_VECTOR check into VLS modes
RISC-V: Add TAREGT_VECTOR check into VLS modes
- - - -
-
-
-
2023-08-12
juzhe.zhong@rivai.ai
New
RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
- - - -
-
-
-
2023-01-20
juzhe.zhong@rivai.ai
New
RISC-V: Add TARGET_MIN_VLEN > 4096 check
RISC-V: Add TARGET_MIN_VLEN > 4096 check
- - - -
-
-
-
2023-07-17
juzhe.zhong@rivai.ai
New
RISC-V: Add Types to Missing Bitmanip Instructions:
RISC-V: Add Types to Missing Bitmanip Instructions:
- - - -
-
-
-
2023-08-21
Edwin Lu
New
RISC-V: Add Types to Un-Typed Risc-v Instructions:
RISC-V: Add Types to Un-Typed Risc-v Instructions:
- - - -
-
-
-
2023-08-31
Edwin Lu
New
RISC-V: Add Types to Un-Typed Sync Instructions:
RISC-V: Add Types to Un-Typed Sync Instructions:
- - - -
-
-
-
2023-08-21
Edwin Lu
New
RISC-V: Add Types to Un-Typed Vector Instructions:
RISC-V: Add Types to Un-Typed Vector Instructions:
- - - -
-
-
-
2023-08-28
Edwin Lu
New
RISC-V: Add VECTOR_ALIGNMENT_REACHABLE && BUILTIN_VECTORIZATION_COST target hook to optimize RVV VL…
RISC-V: Add VECTOR_ALIGNMENT_REACHABLE && BUILTIN_VECTORIZATION_COST target hook to optimize RVV VL…
- - - -
-
-
-
2023-05-15
juzhe.zhong@rivai.ai
New
RISC-V: Add VLS conditional patterns support
RISC-V: Add VLS conditional patterns support
- - - -
-
-
-
2023-09-22
juzhe.zhong@rivai.ai
New
RISC-V: Add VLS mask modes mov patterns[PR111311]
RISC-V: Add VLS mask modes mov patterns[PR111311]
- - - -
-
-
-
2023-09-07
juzhe.zhong@rivai.ai
New
RISC-V: Add VLS modes VEC_PERM support[PR111311]
RISC-V: Add VLS modes VEC_PERM support[PR111311]
- - - -
-
-
-
2023-09-09
juzhe.zhong@rivai.ai
New
RISC-V: Add VLS modes for GNU vectors
RISC-V: Add VLS modes for GNU vectors
- - - -
-
-
-
2023-06-18
juzhe.zhong@rivai.ai
New
RISC-V: Add VLS to mask vec_extract [PR114668].
RISC-V: Add VLS to mask vec_extract [PR114668].
- - - -
-
-
-
2024-04-15
Robin Dapp
New
RISC-V: Add VSETVL testcases for indexed loads/stores.
RISC-V: Add VSETVL testcases for indexed loads/stores.
- - - -
-
-
-
2023-01-29
juzhe.zhong@rivai.ai
New
RISC-V: Add Vector cost model framework for RVV
RISC-V: Add Vector cost model framework for RVV
- - - -
-
-
-
2023-08-31
juzhe.zhong@rivai.ai
New
RISC-V: Add Veyron V1 pipeline description
RISC-V: Add Veyron V1 pipeline description
- - - -
-
-
-
2023-06-07
Raphael Moreira Zinsly
New
RISC-V: Add XiangShan Nanhu microarchitecture.
RISC-V: Add XiangShan Nanhu microarchitecture.
- - - -
-
-
-
2024-02-27
Jiawei
New
RISC-V: Add Z*inx incompatible check in gcc.
RISC-V: Add Z*inx incompatible check in gcc.
- - - -
-
-
-
2023-03-26
Jiawei
New
RISC-V: Add ZVFH extension to the -march= option
RISC-V: Add ZVFH extension to the -march= option
- - - -
-
-
-
2023-05-31
Li, Pan2 via Gcc-patches
New
RISC-V: Add ZVFHMIN autovec block testcase
RISC-V: Add ZVFHMIN autovec block testcase
- - - -
-
-
-
2023-06-12
juzhe.zhong@rivai.ai
New
RISC-V: Add ZVFHMIN extension to the -march= option
RISC-V: Add ZVFHMIN extension to the -march= option
- - - -
-
-
-
2023-05-25
Li, Pan2 via Gcc-patches
New
RISC-V: Add Zawrs ISA extension support
RISC-V: Add Zawrs ISA extension support
- - - -
-
-
-
2022-10-27
Christoph Müllner
New
RISC-V: Add Zvfbfmin extension to the -march= option
RISC-V: Add Zvfbfmin extension to the -march= option
- - 1 -
-
-
-
2023-12-13
Xiao Zeng
New
RISC-V: Add __RISCV_ prefix to VXRM and FRM enum
RISC-V: Add __RISCV_ prefix to VXRM and FRM enum
- - - -
-
-
-
2023-06-01
juzhe.zhong@rivai.ai
New
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid
- - - -
-
-
-
2023-06-02
juzhe.zhong@rivai.ai
New
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid
- - - -
-
-
-
2023-06-01
juzhe.zhong@rivai.ai
New
RISC-V: Add all mask C++ api tests
RISC-V: Add all mask C++ api tests
- - - -
-
-
-
2023-02-16
juzhe.zhong@rivai.ai
New
RISC-V: Add an experimental vector calling convention
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-06-25
Lehua Ding
New
RISC-V: Add and document the "-mno-relax" option
RISC-V: Add and document the "-mno-relax" option
- - - -
-
-
-
2018-03-01
Palmer Dabbelt
New
RISC-V: Add attribute to vtype change only vsetvl
RISC-V: Add attribute to vtype change only vsetvl
- - - -
-
-
-
2023-08-23
juzhe.zhong@rivai.ai
New
RISC-V: Add attributes for VSETVL PASS
RISC-V: Add attributes for VSETVL PASS
- - - -
-
-
-
2022-11-28
juzhe.zhong@rivai.ai
New
RISC-V: Add autovec FP binary operations.
RISC-V: Add autovec FP binary operations.
- - - -
-
-
-
2023-06-14
Robin Dapp
New
RISC-V: Add autovec FP int->float conversion.
RISC-V: Add autovec FP int->float conversion.
- - - -
-
-
-
2023-06-26
Robin Dapp
New
RISC-V: Add autovec FP unary operations.
RISC-V: Add autovec FP unary operations.
- - - -
-
-
-
2023-06-14
Robin Dapp
New
RISC-V: Add autovec FP widening/narrowing.
RISC-V: Add autovec FP widening/narrowing.
- - - -
-
-
-
2023-06-26
Robin Dapp
New
RISC-V: Add autovec sign/zero extension and truncation.
RISC-V: Add autovec sign/zero extension and truncation.
- - - -
-
-
-
2023-05-25
Robin Dapp
New
RISC-V: Add autovect widening/narrowing Integer/FP conversions.
RISC-V: Add autovect widening/narrowing Integer/FP conversions.
- - - -
-
-
-
2023-06-26
Robin Dapp
New
RISC-V: Add avail interface into function_group_info
RISC-V: Add avail interface into function_group_info
- - - -
-
-
-
2023-12-07
Feng Wang
New
RISC-V: Add available vector size for RVV
RISC-V: Add available vector size for RVV
- - - -
-
-
-
2023-10-09
juzhe.zhong@rivai.ai
New
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