diff mbox series

RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes

Message ID 20230120093309.104394-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes | expand

Commit Message

juzhe.zhong@rivai.ai Jan. 20, 2023, 9:33 a.m. UTC 
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
and zve32f. So it makes sense add predicate in the iterators of EEW = 64
vector modes.

gcc/ChangeLog:

        * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.

---
 gcc/config/riscv/vector-iterators.md | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Jeff Law Jan. 22, 2023, 7:28 p.m. UTC | #1 
On 1/20/23 02:33, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
> and zve32f. So it makes sense add predicate in the iterators of EEW = 64
> vector modes.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
OK.

Jeff
Kito Cheng Jan. 27, 2023, 9:59 a.m. UTC | #2 
committed, thanks :)

On Mon, Jan 23, 2023 at 3:29 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:

>
>
> On 1/20/23 02:33, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > According to RVV ISA, RVV doesn't support EEW == 64 vector type for
> zve32x
> > and zve32f. So it makes sense add predicate in the iterators of EEW = 64
> > vector modes.
> >
> > gcc/ChangeLog:
> >
> >          * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32
> predicates.
> OK.
>
> Jeff
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 92c4bd0a6a3..1f29050622b 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -22,7 +22,8 @@ 
   VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32")
   VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32")
   VNx1SI VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32")
-  VNx1DI VNx2DI VNx4DI (VNx8DI "TARGET_MIN_VLEN > 32")
+  (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32")
+  (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -38,7 +39,8 @@ 
   (VNx4QI "TARGET_MIN_VLEN == 32") VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32")
   (VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32")
   (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32")
-  VNx1DI VNx2DI VNx4DI (VNx8DI "TARGET_MIN_VLEN > 32")
+  (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32")
+  (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")