diff mbox series

RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases

Message ID 20230816132010.3628851-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases | expand

Commit Message

juzhe.zhong@rivai.ai Aug. 16, 2023, 1:20 p.m. UTC 
This patch is depending on middle-end patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627621.html

We already had COND_LEN_FNMA/COND_LEN_FMS/COND_FNMS patterns.

Remove TARGET_PREFERRED_ELSE_VALUE since it forbid the COND_LEN_FMS/COND_LEN_FNMS STMT fold.

gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_preferred_else_value): Remove it since it forbid COND_LEN_FMS/COND_LEN_FNMS STMT fold.
        (TARGET_PREFERRED_ELSE_VALUE): Ditto.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Adapt test.
        * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: New test.

---
 gcc/config/riscv/riscv.cc                     | 21 -------------------
 .../rvv/autovec/binop/vadd-rv32gcv-nofm.c     |  7 ++-----
 .../rvv/autovec/binop/vadd-rv64gcv-nofm.c     |  7 ++-----
 .../riscv/rvv/autovec/cond/cond_fadd-1.c      |  3 +--
 .../riscv/rvv/autovec/cond/cond_fadd-2.c      |  3 +--
 .../riscv/rvv/autovec/cond/cond_fadd-3.c      |  3 +--
 .../riscv/rvv/autovec/cond/cond_fadd-4.c      |  3 +--
 .../riscv/rvv/autovec/ternop/ternop_nofm-1.c  |  4 +++-
 .../riscv/rvv/autovec/ternop/ternop_nofm-10.c |  9 ++++++++
 .../riscv/rvv/autovec/ternop/ternop_nofm-11.c |  9 ++++++++
 .../riscv/rvv/autovec/ternop/ternop_nofm-12.c |  6 ++++++
 .../riscv/rvv/autovec/ternop/ternop_nofm-3.c  |  5 ++---
 .../riscv/rvv/autovec/ternop/ternop_nofm-4.c  |  9 ++++++++
 .../riscv/rvv/autovec/ternop/ternop_nofm-5.c  |  9 ++++++++
 .../riscv/rvv/autovec/ternop/ternop_nofm-6.c  |  6 ++++++
 .../riscv/rvv/autovec/ternop/ternop_nofm-7.c  |  9 ++++++++
 .../riscv/rvv/autovec/ternop/ternop_nofm-8.c  |  9 ++++++++
 .../riscv/rvv/autovec/ternop/ternop_nofm-9.c  |  6 ++++++
 .../rvv/autovec/ternop/ternop_nofm_run-10.c   |  4 ++++
 .../rvv/autovec/ternop/ternop_nofm_run-11.c   |  4 ++++
 .../rvv/autovec/ternop/ternop_nofm_run-12.c   |  4 ++++
 .../rvv/autovec/ternop/ternop_nofm_run-4.c    |  4 ++++
 .../rvv/autovec/ternop/ternop_nofm_run-5.c    |  4 ++++
 .../rvv/autovec/ternop/ternop_nofm_run-6.c    |  4 ++++
 .../rvv/autovec/ternop/ternop_nofm_run-7.c    |  4 ++++
 .../rvv/autovec/ternop/ternop_nofm_run-8.c    |  4 ++++
 .../rvv/autovec/ternop/ternop_nofm_run-9.c    |  4 ++++
 27 files changed, 121 insertions(+), 43 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c

Comments

juzhe.zhong@rivai.ai Aug. 24, 2023, 10:53 a.m. UTC | #1 
Ping.

MIddle-end patch:
[PATCH V2] gimple_fold: Support COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS gimple fold (gnu.org)
has been approved and supported.

This patch is pending 8 days.



juzhe.zhong@rivai.ai
 
From: Juzhe-Zhong
Date: 2023-08-16 21:20
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases
This patch is depending on middle-end patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627621.html
 
We already had COND_LEN_FNMA/COND_LEN_FMS/COND_FNMS patterns.
 
Remove TARGET_PREFERRED_ELSE_VALUE since it forbid the COND_LEN_FMS/COND_LEN_FNMS STMT fold.
 
gcc/ChangeLog:
 
        * config/riscv/riscv.cc (riscv_preferred_else_value): Remove it since it forbid COND_LEN_FMS/COND_LEN_FNMS STMT fold.
        (TARGET_PREFERRED_ELSE_VALUE): Ditto.
 
gcc/testsuite/ChangeLog:
 
        * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Adapt test.
        * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: New test.
        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: New test.
 
---
gcc/config/riscv/riscv.cc                     | 21 -------------------
.../rvv/autovec/binop/vadd-rv32gcv-nofm.c     |  7 ++-----
.../rvv/autovec/binop/vadd-rv64gcv-nofm.c     |  7 ++-----
.../riscv/rvv/autovec/cond/cond_fadd-1.c      |  3 +--
.../riscv/rvv/autovec/cond/cond_fadd-2.c      |  3 +--
.../riscv/rvv/autovec/cond/cond_fadd-3.c      |  3 +--
.../riscv/rvv/autovec/cond/cond_fadd-4.c      |  3 +--
.../riscv/rvv/autovec/ternop/ternop_nofm-1.c  |  4 +++-
.../riscv/rvv/autovec/ternop/ternop_nofm-10.c |  9 ++++++++
.../riscv/rvv/autovec/ternop/ternop_nofm-11.c |  9 ++++++++
.../riscv/rvv/autovec/ternop/ternop_nofm-12.c |  6 ++++++
.../riscv/rvv/autovec/ternop/ternop_nofm-3.c  |  5 ++---
.../riscv/rvv/autovec/ternop/ternop_nofm-4.c  |  9 ++++++++
.../riscv/rvv/autovec/ternop/ternop_nofm-5.c  |  9 ++++++++
.../riscv/rvv/autovec/ternop/ternop_nofm-6.c  |  6 ++++++
.../riscv/rvv/autovec/ternop/ternop_nofm-7.c  |  9 ++++++++
.../riscv/rvv/autovec/ternop/ternop_nofm-8.c  |  9 ++++++++
.../riscv/rvv/autovec/ternop/ternop_nofm-9.c  |  6 ++++++
.../rvv/autovec/ternop/ternop_nofm_run-10.c   |  4 ++++
.../rvv/autovec/ternop/ternop_nofm_run-11.c   |  4 ++++
.../rvv/autovec/ternop/ternop_nofm_run-12.c   |  4 ++++
.../rvv/autovec/ternop/ternop_nofm_run-4.c    |  4 ++++
.../rvv/autovec/ternop/ternop_nofm_run-5.c    |  4 ++++
.../rvv/autovec/ternop/ternop_nofm_run-6.c    |  4 ++++
.../rvv/autovec/ternop/ternop_nofm_run-7.c    |  4 ++++
.../rvv/autovec/ternop/ternop_nofm_run-8.c    |  4 ++++
.../rvv/autovec/ternop/ternop_nofm_run-9.c    |  4 ++++
27 files changed, 121 insertions(+), 43 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 49062bef9fc..1c05f15833e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8419,24 +8419,6 @@ riscv_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode,
   return false;
}
-/* Implement TARGET_PREFERRED_ELSE_VALUE.  For binary operations,
-   prefer to use the first arithmetic operand as the else value if
-   the else value doesn't matter, since that exactly matches the RVV
-   destructive merging form.  For ternary operations we could either
-   pick the first operand and use VMADD-like instructions or the last
-   operand and use VMACC-like instructions; the latter seems more
-   natural.
-
-   TODO: Currently, the return value is not ideal for RVV since it will
-   let VSETVL PASS use MU or TU. We will suport undefine value that allows
-   VSETVL PASS use TA/MA in the future.  */
-
-static tree
-riscv_preferred_else_value (unsigned, tree, unsigned int nops, tree *ops)
-{
-  return nops == 3 ? ops[2] : ops[0];
-}
-
static bool
riscv_frame_pointer_required (void)
{
@@ -8747,9 +8729,6 @@ riscv_frame_pointer_required (void)
#undef TARGET_VECTORIZE_VEC_PERM_CONST
#define TARGET_VECTORIZE_VEC_PERM_CONST riscv_vectorize_vec_perm_const
-#undef TARGET_PREFERRED_ELSE_VALUE
-#define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value
-
#undef TARGET_FRAME_POINTER_REQUIRED
#define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
index 069bc690697..60c760d939d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
@@ -5,9 +5,6 @@
/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
-/* { dg-final { scan-assembler-times {\tvfadd\.vv} 7 } } */
-/* There are 2 MINUS operations.  */
-/* { dg-final { scan-assembler-times {\tvfsub\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
-/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 7 "optimized" } } */
-/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 2 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
index 07fa54878cc..86d5283c4b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
@@ -5,9 +5,6 @@
/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
-/* { dg-final { scan-assembler-times {\tvfadd\.vv} 7 } } */
-/* There are 2 MINUS operations.  */
-/* { dg-final { scan-assembler-times {\tvfsub\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
-/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 7 "optimized" } } */
-/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 2 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
index 11c5c54309b..c9d14f27e5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
@@ -29,5 +29,4 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
-/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
index e992459a7b0..21f9f9f9107 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
@@ -28,5 +28,4 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
-/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
index f940d64742e..f71dbaa80ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
@@ -29,5 +29,4 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
-/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
index e4f3e823819..ffbe9a47cd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
@@ -29,5 +29,4 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
-/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
index d6085043af4..3f7febc4565 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
@@ -3,5 +3,7 @@
#include "ternop-1.c"
-/* { dg-final { scan-assembler-not {\tvmv} } } */
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
/* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
new file mode 100644
index 00000000000..27981fc034a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-10.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
new file mode 100644
index 00000000000..fcbed651be9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-11.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
new file mode 100644
index 00000000000..0ce468d60de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
+
+#include "ternop-12.c"
+
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
index 63cd4aeb705..429cff9d4e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
@@ -4,6 +4,5 @@
#include "ternop-3.c"
/* { dg-final { scan-assembler-times {\tvmacc\.vv} 8 } } */
-/* { dg-final { scan-assembler-times {\tvfmacc\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmv} 11 } } */
-/* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 6 "optimized" } } */
+/* { dg-final { scan-assembler-times {\tvfmacc\.vv} 9 } } */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
new file mode 100644
index 00000000000..9ec7527553c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-4.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
new file mode 100644
index 00000000000..9aa8e83f7a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-5.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
new file mode 100644
index 00000000000..cc4f7f2c6e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
+
+#include "ternop-6.c"
+
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
new file mode 100644
index 00000000000..7100fe77767
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-7.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
new file mode 100644
index 00000000000..228ada73935
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-8.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
new file mode 100644
index 00000000000..5ab22287741
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
+
+#include "ternop-9.c"
+
+/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
new file mode 100644
index 00000000000..2e11144c0f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
new file mode 100644
index 00000000000..bdbbb763d2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
new file mode 100644
index 00000000000..77d92ddb59c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
new file mode 100644
index 00000000000..d595b60aeb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
new file mode 100644
index 00000000000..a5373377db6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
new file mode 100644
index 00000000000..844b563d6d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
new file mode 100644
index 00000000000..bd7fcfcce3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
new file mode 100644
index 00000000000..90300cce23b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
new file mode 100644
index 00000000000..7e752afe367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-9.c"
Robin Dapp Aug. 24, 2023, 11:03 a.m. UTC | #2 
OK.

Regards
 Robin
Li, Pan2 via Gcc-patches Aug. 24, 2023, 11:36 a.m. UTC | #3 
Committed, thanks Robin.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Robin Dapp via Gcc-patches
Sent: Thursday, August 24, 2023 7:03 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: rdapp.gcc@gmail.com; kito.cheng <kito.cheng@gmail.com>; kito.cheng <kito.cheng@sifive.com>; Jeff Law <jeffreyalaw@gmail.com>
Subject: Re: [PATCH] RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases

OK.

Regards
 Robin
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 49062bef9fc..1c05f15833e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8419,24 +8419,6 @@  riscv_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode,
   return false;
 }
 
-/* Implement TARGET_PREFERRED_ELSE_VALUE.  For binary operations,
-   prefer to use the first arithmetic operand as the else value if
-   the else value doesn't matter, since that exactly matches the RVV
-   destructive merging form.  For ternary operations we could either
-   pick the first operand and use VMADD-like instructions or the last
-   operand and use VMACC-like instructions; the latter seems more
-   natural.
-
-   TODO: Currently, the return value is not ideal for RVV since it will
-   let VSETVL PASS use MU or TU. We will suport undefine value that allows
-   VSETVL PASS use TA/MA in the future.  */
-
-static tree
-riscv_preferred_else_value (unsigned, tree, unsigned int nops, tree *ops)
-{
-  return nops == 3 ? ops[2] : ops[0];
-}
-
 static bool
 riscv_frame_pointer_required (void)
 {
@@ -8747,9 +8729,6 @@  riscv_frame_pointer_required (void)
 #undef TARGET_VECTORIZE_VEC_PERM_CONST
 #define TARGET_VECTORIZE_VEC_PERM_CONST riscv_vectorize_vec_perm_const
 
-#undef TARGET_PREFERRED_ELSE_VALUE
-#define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value
-
 #undef TARGET_FRAME_POINTER_REQUIRED
 #define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
index 069bc690697..60c760d939d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
@@ -5,9 +5,6 @@ 
 
 /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
 /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
-/* { dg-final { scan-assembler-times {\tvfadd\.vv} 7 } } */
-/* There are 2 MINUS operations.  */
-/* { dg-final { scan-assembler-times {\tvfsub\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
 
-/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 7 "optimized" } } */
-/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 2 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
index 07fa54878cc..86d5283c4b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
@@ -5,9 +5,6 @@ 
 
 /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
 /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
-/* { dg-final { scan-assembler-times {\tvfadd\.vv} 7 } } */
-/* There are 2 MINUS operations.  */
-/* { dg-final { scan-assembler-times {\tvfsub\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
 
-/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 7 "optimized" } } */
-/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 2 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
index 11c5c54309b..c9d14f27e5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
@@ -29,5 +29,4 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
-/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
index e992459a7b0..21f9f9f9107 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
@@ -28,5 +28,4 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
-/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
index f940d64742e..f71dbaa80ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
@@ -29,5 +29,4 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
-/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
index e4f3e823819..ffbe9a47cd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
@@ -29,5 +29,4 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
-/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
index d6085043af4..3f7febc4565 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
@@ -3,5 +3,7 @@ 
 
 #include "ternop-1.c"
 
-/* { dg-final { scan-assembler-not {\tvmv} } } */
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
 /* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
new file mode 100644
index 00000000000..27981fc034a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-10.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
new file mode 100644
index 00000000000..fcbed651be9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-11.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
new file mode 100644
index 00000000000..0ce468d60de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
+
+#include "ternop-12.c"
+
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
index 63cd4aeb705..429cff9d4e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
@@ -4,6 +4,5 @@ 
 #include "ternop-3.c"
 
 /* { dg-final { scan-assembler-times {\tvmacc\.vv} 8 } } */
-/* { dg-final { scan-assembler-times {\tvfmacc\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmv} 11 } } */
-/* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 6 "optimized" } } */
+/* { dg-final { scan-assembler-times {\tvfmacc\.vv} 9 } } */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
new file mode 100644
index 00000000000..9ec7527553c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-4.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
new file mode 100644
index 00000000000..9aa8e83f7a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-5.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
new file mode 100644
index 00000000000..cc4f7f2c6e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
+
+#include "ternop-6.c"
+
+/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
new file mode 100644
index 00000000000..7100fe77767
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-7.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 3 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
new file mode 100644
index 00000000000..228ada73935
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include "ternop-8.c"
+
+/* TODO: we don't have undefine IR for COND_LEN_* operations,
+    which will produce redundant move instructions here.
+    Will add assembler-not check of 'vmv' instructions in the future.  */
+/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
new file mode 100644
index 00000000000..5ab22287741
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
+
+#include "ternop-9.c"
+
+/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 9 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
new file mode 100644
index 00000000000..2e11144c0f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
new file mode 100644
index 00000000000..bdbbb763d2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
new file mode 100644
index 00000000000..77d92ddb59c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
new file mode 100644
index 00000000000..d595b60aeb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
new file mode 100644
index 00000000000..a5373377db6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
new file mode 100644
index 00000000000..844b563d6d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
new file mode 100644
index 00000000000..bd7fcfcce3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
new file mode 100644
index 00000000000..90300cce23b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
new file mode 100644
index 00000000000..7e752afe367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
@@ -0,0 +1,4 @@ 
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop_run-9.c"