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Patrick O'Neill
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Apply
«
1
2
»
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
RISC-V: Require a extension for ztso testcases with atomic insns
RISC-V: Require a extension for ztso testcases with atomic insns
1 - 1 -
-
-
-
2024-03-21
Patrick O'Neill
New
[RFC,3/3] RISC-V: Add Zalrsc amo-op patterns
[RFC,1/3] RISC-V: Add basic Zaamo and Zalrsc support
- - - -
-
-
-
2024-02-08
Patrick O'Neill
New
[RFC,2/3] RISC-V: Add Zalrsc and Zaamo testsuite support
[RFC,1/3] RISC-V: Add basic Zaamo and Zalrsc support
- - - -
-
-
-
2024-02-08
Patrick O'Neill
New
[RFC,1/3] RISC-V: Add basic Zaamo and Zalrsc support
[RFC,1/3] RISC-V: Add basic Zaamo and Zalrsc support
- - - -
-
-
-
2024-02-08
Patrick O'Neill
New
RISC-V: Add require-effective-target to pr113429 testcase
RISC-V: Add require-effective-target to pr113429 testcase
- - - -
-
-
-
2024-01-27
Patrick O'Neill
New
[Committed] RISC-V: Add regression test for vsetvl bug pr113429
[Committed] RISC-V: Add regression test for vsetvl bug pr113429
- - - -
-
-
-
2024-01-24
Patrick O'Neill
New
RISC-V: Add regression test for vsetvl bug pr113429
RISC-V: Add regression test for vsetvl bug pr113429
- - - -
-
-
-
2024-01-24
Patrick O'Neill
New
RISC-V: Add -fno-vect-cost-model to pr112773 testcase
RISC-V: Add -fno-vect-cost-model to pr112773 testcase
- - - -
-
-
-
2023-12-14
Patrick O'Neill
New
[Committed] RISC-V: Fix ICE in non-canonical march parsing
[Committed] RISC-V: Fix ICE in non-canonical march parsing
- - - -
-
-
-
2023-11-15
Patrick O'Neill
New
RISC-V: Fix ICE in non-canonical march parsing
RISC-V: Fix ICE in non-canonical march parsing
- - - -
-
-
-
2023-11-15
Patrick O'Neill
New
g++: Add require-effective-target to multi-input file testcase pr95401.cc
g++: Add require-effective-target to multi-input file testcase pr95401.cc
- - - -
-
-
-
2023-11-03
Patrick O'Neill
New
g++: Rely on dg-do-what-default to avoid running pr102788.cc on non-vector targets
g++: Rely on dg-do-what-default to avoid running pr102788.cc on non-vector targets
- - - -
-
-
-
2023-11-02
Patrick O'Neill
New
gfortran: Rely on dg-do-what-default to avoid running pr85853.f90, pr107254.f90 and vect-alias-chec…
gfortran: Rely on dg-do-what-default to avoid running pr85853.f90, pr107254.f90 and vect-alias-chec…
- - - -
-
-
-
2023-11-02
Patrick O'Neill
New
[v2] RISC-V: Use riscv_subword_address for atomic_test_and_set
[v2] RISC-V: Use riscv_subword_address for atomic_test_and_set
- - - -
-
-
-
2023-11-01
Patrick O'Neill
New
RISC-V: Use riscv_subword_address for atomic_test_and_set
RISC-V: Use riscv_subword_address for atomic_test_and_set
- - - -
-
-
-
2023-11-01
Patrick O'Neill
New
[v2] RISC-V: Enable ztso tests on rv32
[v2] RISC-V: Enable ztso tests on rv32
- - - -
-
-
-
2023-10-31
Patrick O'Neill
New
[2/2] RISC-V: Require a extension for testcases with atomic insns
[1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores
- - - -
-
-
-
2023-10-31
Patrick O'Neill
New
[1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores
[1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores
- - - -
-
-
-
2023-10-31
Patrick O'Neill
New
RISC-V: Enable ztso tests on rv32
RISC-V: Enable ztso tests on rv32
- - - -
-
-
-
2023-10-31
Patrick O'Neill
New
RISC-V: Make rv32i_zcmp testcase more robust
RISC-V: Make rv32i_zcmp testcase more robust
- - - -
-
-
-
2023-10-30
Patrick O'Neill
New
RISC-V: Make stack_save_restore_2 more robust
RISC-V: Make stack_save_restore_2 more robust
- - - -
-
-
-
2023-10-27
Patrick O'Neill
New
RISC-V: Pass abi to g++ rvv testsuite
RISC-V: Pass abi to g++ rvv testsuite
- - - -
-
-
-
2023-10-26
Patrick O'Neill
New
[v2] RISC-V: Use stdint-gcc.h in rvv testsuite
[v2] RISC-V: Use stdint-gcc.h in rvv testsuite
- - - -
-
-
-
2023-10-05
Patrick O'Neill
New
[v2] RISC-V: Test memcpy inlined on riscv_v
[v2] RISC-V: Test memcpy inlined on riscv_v
- - - -
-
-
-
2023-10-04
Patrick O'Neill
New
RISC-V: xfail gcc.dg/pr90263.c for riscv_v
RISC-V: xfail gcc.dg/pr90263.c for riscv_v
- - - -
-
-
-
2023-10-04
Patrick O'Neill
New
[RFC,gcc13,backport,3/3,RISCV,committed] Remove spurious newline in ztso sequence
Add Ztso atomic mappings
- - - -
-
-
-
2023-10-03
Patrick O'Neill
New
[RFC,gcc13,backport,2/3] RISC-V: Specify -mabi for ztso testcases
Add Ztso atomic mappings
- - - -
-
-
-
2023-10-03
Patrick O'Neill
New
[RFC,gcc13,backport,1/3] RISC-V: Add Ztso atomic mappings
Add Ztso atomic mappings
- - - -
-
-
-
2023-10-03
Patrick O'Neill
New
RISC-V: Unescape chars in pr111566.f90 test
RISC-V: Unescape chars in pr111566.f90 test
- - - -
-
-
-
2023-10-03
Patrick O'Neill
New
[Committed] RISC-V: Use safe_grow_cleared for vector info [PR111469]
[Committed] RISC-V: Use safe_grow_cleared for vector info [PR111469]
- - - -
-
-
-
2023-09-30
Patrick O'Neill
New
RISC-V: Use safe_grow_cleared for vector info [PR111469]
RISC-V: Use safe_grow_cleared for vector info [PR111469]
- - - -
-
-
-
2023-09-30
Patrick O'Neill
New
RISC-V: Specify -mabi=lp64d in wredsum_vlmax.c testcase
RISC-V: Specify -mabi=lp64d in wredsum_vlmax.c testcase
- - - -
-
-
-
2023-09-29
Patrick O'Neill
New
RISC-V: Use stdint-gcc.h in rvv testsuite
RISC-V: Use stdint-gcc.h in rvv testsuite
- - - -
-
-
-
2023-09-26
Patrick O'Neill
New
RISC-V: Remove math.h import to resolve missing stubs failures
RISC-V: Remove math.h import to resolve missing stubs failures
- - - 2
-
-
-
2023-09-20
Patrick O'Neill
New
[Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap
[Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap
- - - 1
-
-
-
2023-09-19
Patrick O'Neill
New
RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap
RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap
- - - 2
-
-
-
2023-09-19
Patrick O'Neill
New
check_GNU_style.py: Skip .md square bracket linting
check_GNU_style.py: Skip .md square bracket linting
- - - -
-
-
-
2023-09-12
Patrick O'Neill
New
RISC-V: Move vector-abi testcases into rvv/base folder
RISC-V: Move vector-abi testcases into rvv/base folder
- - 1 -
-
-
-
2023-08-24
Patrick O'Neill
New
[v2] RISCV: Add rotate immediate regression test
[v2] RISCV: Add rotate immediate regression test
- - - -
-
-
-
2023-08-17
Patrick O'Neill
New
RISC-V: Add rotate immediate regression test
RISC-V: Add rotate immediate regression test
- - - -
-
-
-
2023-08-16
Patrick O'Neill
New
RISC-V: Specify -mabi for ztso testcases
RISC-V: Specify -mabi for ztso testcases
- - - -
-
-
-
2023-08-11
Patrick O'Neill
New
[v3] RISC-V: Add Ztso atomic mappings
[v3] RISC-V: Add Ztso atomic mappings
- - 1 -
-
-
-
2023-08-08
Patrick O'Neill
New
[Committed] RISC-V: Specify -mabi in rv64 autovec testcase
[Committed] RISC-V: Specify -mabi in rv64 autovec testcase
- - - -
-
-
-
2023-07-28
Patrick O'Neill
New
[gcc13,backport,12/12] riscv: fix error: control reaches end of non-void function
RISC-V: Implement ISA Manual Table A.6 Mappings
- 1 - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,11/12] RISC-V: Table A.6 conformance tests
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,10/12] RISC-V: Weaken atomic loads
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,09/12] RISC-V: Weaken mem_thread_fence
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,08/12] RISC-V: Weaken LR/SC pairs
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,07/12] RISC-V: Eliminate AMO op fences
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,06/12] RISC-V: Strengthen atomic stores
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,05/12] RISC-V: Add AMO release bits
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,04/12] RISC-V: Enforce atomic compare_exchange SEQ_CST
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,03/12] RISC-V: Enforce subword atomic LR/SC SEQ_CST
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,02/12] RISC-V: Enforce Libatomic LR/SC SEQ_CST
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[gcc13,backport,01/12] RISC-V: Eliminate SYNC memory models
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-07-25
Patrick O'Neill
New
[RFC,v2] RISC-V: Add Ztso atomic mappings
[RFC,v2] RISC-V: Add Ztso atomic mappings
- - - -
-
-
-
2023-07-17
Patrick O'Neill
New
[RFC] RISC-V: Add proposed Ztso atomic mappings
[RFC] RISC-V: Add proposed Ztso atomic mappings
- - - -
-
-
-
2023-05-05
Patrick O'Neill
New
[gcc13,backport] RISCV: Inline subword atomic ops
[gcc13,backport] RISCV: Inline subword atomic ops
- - - -
-
-
-
2023-05-03
Patrick O'Neill
New
[Committed,11/11] RISC-V: Table A.6 conformance tests
Untitled series #353203
- - - -
-
-
-
2023-05-02
Patrick O'Neill
New
RISC-V: Name newly added flags in changelog
RISC-V: Name newly added flags in changelog
- - - -
-
-
-
2023-05-01
Patrick O'Neill
New
[v5,11/11] RISC-V: Table A.6 conformance tests
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,10/11] RISC-V: Weaken atomic loads
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,09/11] RISC-V: Weaken mem_thread_fence
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,08/11] RISC-V: Weaken LR/SC pairs
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,07/11] RISC-V: Eliminate AMO op fences
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,06/11] RISC-V: Strengthen atomic stores
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,05/11] RISC-V: Add AMO release bits
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,04/11] RISC-V: Enforce atomic compare_exchange SEQ_CST
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,03/11] RISC-V: Enforce subword atomic LR/SC SEQ_CST
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,02/11] RISC-V: Enforce Libatomic LR/SC SEQ_CST
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v5,01/11] RISC-V: Eliminate SYNC memory models
RISC-V: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-27
Patrick O'Neill
New
[v2] RISC-V: Fix sync.md and riscv.cc whitespace errors
[v2] RISC-V: Fix sync.md and riscv.cc whitespace errors
- - - -
-
-
-
2023-04-26
Patrick O'Neill
New
RISC-V: Fix sync.md and riscv.cc whitespace errors
RISC-V: Fix sync.md and riscv.cc whitespace errors
- - - -
-
-
-
2023-04-26
Patrick O'Neill
New
[committed] RISCV: Inline subword atomic ops
[committed] RISCV: Inline subword atomic ops
- - - -
-
-
-
2023-04-26
Patrick O'Neill
New
MAINTAINERS: Add myself to write after approval
MAINTAINERS: Add myself to write after approval
1 - - -
-
-
-
2023-04-26
Patrick O'Neill
New
[v7] RISCV: Inline subword atomic ops
[v7] RISCV: Inline subword atomic ops
- - - -
-
-
-
2023-04-18
Patrick O'Neill
New
[v6] RISCV: Inline subword atomic ops
[v6] RISCV: Inline subword atomic ops
- - - -
-
-
-
2023-04-18
Patrick O'Neill
New
[v5] RISCV: Inline subword atomic ops
[v5] RISCV: Inline subword atomic ops
- - - -
-
-
-
2023-04-18
Patrick O'Neill
New
[v4,10/10] RISCV: Table A.6 conformance tests
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,09/10] RISCV: Weaken atomic loads
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,08/10] RISCV: Weaken mem_thread_fence
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,07/10] RISCV: Weaken compare_exchange LR/SC pairs
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,06/10] RISCV: Eliminate AMO op fences
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,05/10] RISCV: Strengthen atomic stores
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,04/10] RISCV: Add AMO release bits
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,03/10] RISCV: Enforce atomic compare_exchange SEQ_CST
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v4,01/10] RISCV: Eliminate SYNC memory models
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-14
Patrick O'Neill
New
[v3,10/10] RISCV: Table A.6 conformance tests
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
-
-
-
2023-04-10
Patrick O'Neill
New
[v3,09/10] RISCV: Weaken atomic loads
RISCV: Implement ISA Manual Table A.6 Mappings
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2023-04-10
Patrick O'Neill
New
[v3,08/10] RISCV: Weaken mem_thread_fence
RISCV: Implement ISA Manual Table A.6 Mappings
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2023-04-10
Patrick O'Neill
New
[v3,07/10] RISCV: Weaken compare_exchange LR/SC pairs
RISCV: Implement ISA Manual Table A.6 Mappings
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2023-04-10
Patrick O'Neill
New
[v3,06/10] RISCV: Eliminate AMO op fences
RISCV: Implement ISA Manual Table A.6 Mappings
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2023-04-10
Patrick O'Neill
New
[v3,05/10] RISCV: Strengthen atomic stores
RISCV: Implement ISA Manual Table A.6 Mappings
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2023-04-10
Patrick O'Neill
New
[v3,04/10] RISCV: Add AMO release bits
RISCV: Implement ISA Manual Table A.6 Mappings
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2023-04-10
Patrick O'Neill
New
[v3,03/10] RISCV: Enforce atomic compare_exchange SEQ_CST
RISCV: Implement ISA Manual Table A.6 Mappings
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2023-04-10
Patrick O'Neill
New
[v3,02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST
RISCV: Implement ISA Manual Table A.6 Mappings
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2023-04-10
Patrick O'Neill
New
[v3,01/10] RISCV: Eliminate SYNC memory models
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
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2023-04-10
Patrick O'Neill
New
[v2,8/8] RISCV: Weaken mem_thread_fence
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
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2023-04-05
Patrick O'Neill
New
[v2,7/8] RISCV: Weaken atomic stores
RISCV: Implement ISA Manual Table A.6 Mappings
- - - -
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-
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2023-04-05
Patrick O'Neill
New
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