| Message ID | 20230812023002.238780-1-juzhe.zhong@rivai.ai |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Add TAREGT_VECTOR check into VLS modes | expand |
On 8/11/23 20:30, Juzhe-Zhong wrote: > This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 > > This is caused VLS modes incorrect codes int register allocation. > > The original case trigger the ICE is fortran code but I can reproduce > with a C code. > > PR target/110994 > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test. OK jeff
Committed, thanks Jeff. Pan -----Original Message----- From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches Sent: Saturday, August 12, 2023 11:57 AM To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com; kito.cheng@gmail.com; rdapp.gcc@gmail.com Subject: Re: [PATCH] RISC-V: Add TAREGT_VECTOR check into VLS modes On 8/11/23 20:30, Juzhe-Zhong wrote: > This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 > > This is caused VLS modes incorrect codes int register allocation. > > The original case trigger the ICE is fortran code but I can reproduce > with a C code. > > PR target/110994 > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test. OK jeff
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index d6d785d0075..aeea805b342 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -300,6 +300,7 @@ enum riscv_entity /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode is the highest priority choice and should not conflict with VLS modes. */ -#define TARGET_VECTOR_VLS (riscv_autovec_preference == RVV_SCALABLE) +#define TARGET_VECTOR_VLS \ + (TARGET_VECTOR && riscv_autovec_preference == RVV_SCALABLE) #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c new file mode 100644 index 00000000000..fcacc78b7a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */ + +#include "def.h" + +void foo (int8_t *in, int8_t *out) +{ + v4qi v = *(v4qi*)in; + *(v4qi*)out = v; +}
This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 This is caused VLS modes incorrect codes int register allocation. The original case trigger the ICE is fortran code but I can reproduce with a C code. PR target/110994 gcc/ChangeLog: * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test. --- gcc/config/riscv/riscv-opts.h | 3 ++- .../gcc.target/riscv/rvv/autovec/vls/pr110994.c | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c