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RISC-V: Add attribute to vtype change only vsetvl

Message ID 20230823021106.3498134-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Add attribute to vtype change only vsetvl | expand

Commit Message

juzhe.zhong@rivai.ai Aug. 23, 2023, 2:11 a.m. UTC 
This patch is prepare patch for VSETVL PASS.

Commited.

gcc/ChangeLog:

	* config/riscv/vector.md: Add attribute.

---
 gcc/config/riscv/vector.md | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
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Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index e772e79057d..6ceae25dbed 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1363,7 +1363,11 @@ 
   "TARGET_VECTOR"
   "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
   [(set_attr "type" "vsetvl")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "SI")
+   (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
+   (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
+   (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
+   (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
 
 ;; vsetvl zero,rs1,vtype instruction.
 ;; The reason we need this pattern since we should avoid setting X0 register