Show patches with: Submitter = Weiwei Li       |    State = Action Required       |    Archived = No       |   599 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[01/14] target/riscv: Fix the relationship between Zfhmin and Zfh target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[04/14] target/riscv: Add cfg properties for Zv* extension target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[05/14] target/riscv: Fix relationship between V, Zve*, F and D target/riscv: Some updates to float point related extensions - - - - --- 2023-02-14 Weiwei Li New
[06/14] target/riscv: Add propertie check for Zvfh{min} extensions target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[07/14] target/riscv: Indent fixes in cpu.c target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[08/14] target/riscv: Simplify check for Zve32f and Zve64f target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[1/1] MAINTAINERS: update mail address for Weiwei Li [1/1] MAINTAINERS: update mail address for Weiwei Li - - 4 - --- 2023-10-30 Weiwei Li New
[1/1] hw/riscv: Add signature dump function for spike to run ACT tests hw/riscv: Add ACT related support - - 1 - --- 2023-03-06 Weiwei Li New
[1/2] target/riscv: Add additional xlen for address when MPRV=1 target/riscv: Fix the xlen for data address when MPRV=1 - - 1 - --- 2023-06-14 Weiwei Li New
[1/2] target/riscv: Add set_implicit_extensions_from_ext() function target/riscv: Separate implicitly-enabled and explicitly-enabled extensions - - 2 - --- 2023-04-10 Weiwei Li New
[1/2] target/riscv: Fix the mstatus.MPP value after executing MRET target/riscv: Fix mstatus.MPP related support - - 1 - --- 2023-03-30 Weiwei Li New
[1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize [1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize - - - - --- 2022-05-16 Weiwei Li New
[1/2] target/riscv: optimize condition assign for scale < 0 [1/2] target/riscv: optimize condition assign for scale < 0 1 - 1 - --- 2022-03-25 Weiwei Li New
[1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig target/riscv: Some CPURISCVState related cleanup and simplification - - 2 - --- 2023-03-09 Weiwei Li New
[1/4] target/riscv: Make MPV only work when MPP != PRV_M target/riscv: Fix mstatus related problems - - 3 - --- 2023-05-29 Weiwei Li New
[1/5] target/riscv: Fix effective address for pointer mask target/riscv: Fix pointer mask related support - - 1 - --- 2023-03-27 Weiwei Li New
[1/6] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions target/riscv: Add support for Svadu extension - - 1 - --- 2023-02-24 Weiwei Li New
[1/6] target/riscv: Update pmp_get_tlb_size() target/riscv: Fix PMP related problem - - 1 - --- 2023-04-13 Weiwei Li New
[1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} support subsets of Float-Point in Integer Registers extensions - - 1 - --- 2021-12-24 Weiwei Li New
[1/6] target/riscv: add check for supported privilege modes conbinations Improve the U/S/H extension related check - - 1 - --- 2022-07-10 Weiwei Li New
[1/7] disas: Change type of disassemble_info.target_info to pointer Add support for extension specific disas - - 1 - --- 2023-05-19 Weiwei Li New
[1/7] target/riscv: Fix target address to update badaddr target/riscv: Add support for PC-relative translation - - 2 - --- 2023-04-09 Weiwei Li New
[1/8] target/riscv: Remove redundant call to riscv_cpu_virt_enabled target/riscv: Simplification for RVH related check and code style fix - - 1 - --- 2023-03-24 Weiwei Li New
[10/14] target/riscv: Remove rebundunt check for zve32f and zve64f target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[11/14] target/riscv: Add support for Zvfh/zvfhmin extensions target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64 target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[14/14] target/riscv: Expose properties for Zv* extension target/riscv: Some updates to float point related extensions - - 1 - --- 2023-02-14 Weiwei Li New
[2/2] target/riscv: Add ext_z*_enabled for implicitly enabled extensions target/riscv: Separate implicitly-enabled and explicitly-enabled extensions - - - - --- 2023-04-10 Weiwei Li New
[2/2] target/riscv: Legalize MPP value in write_mstatus target/riscv: Fix mstatus.MPP related support - - - - --- 2023-03-30 Weiwei Li New
[2/2] target/riscv: disable zb* extensions by default [1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize - - - - --- 2022-05-16 Weiwei Li New
[2/2] target/riscv: optimize helper for vmv<nr>r.v [1/2] target/riscv: optimize condition assign for scale < 0 - - 2 - --- 2022-03-25 Weiwei Li New
[2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV target/riscv: Fix the xlen for data address when MPRV=1 - - 1 - --- 2023-06-14 Weiwei Li New
[2/4] target/riscv: Remove check on mode for MPRV target/riscv: Fix mstatus related problems - - 1 - --- 2023-05-29 Weiwei Li New
[2/4] target/riscv: Simplify getting RISCVCPU pointer from env target/riscv: Some CPURISCVState related cleanup and simplification - - 3 - --- 2023-03-09 Weiwei Li New
[2/5] target/riscv: Use sign-extended data address when xl = 32 target/riscv: Fix pointer mask related support - - 1 - --- 2023-03-27 Weiwei Li New
[2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg target/riscv: Add support for Svadu extension - - 1 - --- 2023-02-24 Weiwei Li New
[2/6] target/riscv: H extension depends on I extension Improve the U/S/H extension related check - - 1 - --- 2022-07-10 Weiwei Li New
[2/6] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp target/riscv: Fix PMP related problem - - 1 - --- 2023-04-13 Weiwei Li New
[2/6] target/riscv: add support for unique fpr read/write with support for zfinx support subsets of Float-Point in Integer Registers extensions - - - - --- 2021-12-24 Weiwei Li New
[2/7] target/riscv: Introduce cur_insn_len into DisasContext target/riscv: Add support for PC-relative translation - - - - --- 2023-04-09 Weiwei Li New
[2/7] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Add support for extension specific disas - - 1 - --- 2023-05-19 Weiwei Li New
[2/8] target/riscv: Remove redundant check on RVH target/riscv: Simplification for RVH related check and code style fix - - 1 - --- 2023-03-24 Weiwei Li New
[3/4] target/riscv: Simplify type conversion for CPURISCVState target/riscv: Some CPURISCVState related cleanup and simplification - - 2 - --- 2023-03-09 Weiwei Li New
[3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled target/riscv: Fix mstatus related problems - - 2 - --- 2023-05-29 Weiwei Li New
[3/5] target/riscv: Fix pointer mask transformation for vector address target/riscv: Fix pointer mask related support - - 2 - --- 2023-03-27 Weiwei Li New
[3/6] target/riscv: Add csr support for svadu target/riscv: Add support for Svadu extension - - 1 - --- 2023-02-24 Weiwei Li New
[3/6] target/riscv: add support for zfinx support subsets of Float-Point in Integer Registers extensions - - - - --- 2021-12-24 Weiwei Li New
[3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table Improve the U/S/H extension related check - - - - --- 2022-07-10 Weiwei Li New
[3/6] target/riscv: flush tlb when pmpaddr is updated target/riscv: Fix PMP related problem - - 1 - --- 2023-04-13 Weiwei Li New
[3/7] disas/riscv.c: Support disas for Zcm* extensions Add support for extension specific disas - - 1 - --- 2023-05-19 Weiwei Li New
[3/7] target/riscv: Change gen_goto_tb to work on displacements target/riscv: Add support for PC-relative translation - - - - --- 2023-04-09 Weiwei Li New
[3/8] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled target/riscv: Simplification for RVH related check and code style fix - - 1 - --- 2023-03-24 Weiwei Li New
[4/4] target/riscv: Remove redundant assignment to SXL target/riscv: Fix mstatus related problems - - 3 - --- 2023-05-29 Weiwei Li New
[4/4] target/riscv: Simplify arguments for riscv_csrrw_check target/riscv: Some CPURISCVState related cleanup and simplification - - 3 - --- 2023-03-09 Weiwei Li New
[4/5] target/riscv: take xl into consideration for vector address target/riscv: Fix pointer mask related support - - 1 - --- 2023-03-27 Weiwei Li New
[4/6] target/riscv: Add *envcfg.PBMTE related check in address translation target/riscv: Add support for Svadu extension - - 1 - --- 2023-02-24 Weiwei Li New
[4/6] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes target/riscv: Fix PMP related problem - - 1 - --- 2023-04-13 Weiwei Li New
[4/6] target/riscv: add check for csrs existed with U extension Improve the U/S/H extension related check - - 1 - --- 2022-07-10 Weiwei Li New
[4/6] target/riscv: add support for zdinx support subsets of Float-Point in Integer Registers extensions - - - - --- 2021-12-24 Weiwei Li New
[4/7] disas/riscv.c: Support disas for Z*inx extensions Add support for extension specific disas - - 1 - --- 2023-05-19 Weiwei Li New
[4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc target/riscv: Add support for PC-relative translation - - - - --- 2023-04-09 Weiwei Li New
[4/8] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled target/riscv: Simplification for RVH related check and code style fix - - 1 - --- 2023-03-24 Weiwei Li New
[5/5] target/riscv: Add pointer mask support for instruction fetch target/riscv: Fix pointer mask related support - - 2 - --- 2023-03-27 Weiwei Li New
[5/6] target/riscv: Add *envcfg.HADE related check in address translation target/riscv: Add support for Svadu extension - - 1 - --- 2023-02-24 Weiwei Li New
[5/6] target/riscv: add support for zhinx/zhinxmin support subsets of Float-Point in Integer Registers extensions - - - - --- 2021-12-24 Weiwei Li New
[5/6] target/riscv: fix checks in hmode/hmode32 Improve the U/S/H extension related check - - - - --- 2022-07-10 Weiwei Li New
[5/6] target/riscv: flush tb when PMP entry changes target/riscv: Fix PMP related problem - - - - --- 2023-04-13 Weiwei Li New
[5/7] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Add support for extension specific disas - - 1 - --- 2023-05-19 Weiwei Li New
[5/7] target/riscv: Use true diff for gen_pc_plus_diff target/riscv: Add support for PC-relative translation - - - - --- 2023-04-09 Weiwei Li New
[5/8] target/riscv: Remove redundant parentheses target/riscv: Simplification for RVH related check and code style fix - - 1 - --- 2023-03-24 Weiwei Li New
[6/6] accel/tcg: Remain TLB_INVALID_MASK in the address when TLB is re-filled target/riscv: Fix PMP related problem - - - - --- 2023-04-13 Weiwei Li New
[6/6] target/riscv: Export Svadu property target/riscv: Add support for Svadu extension - - 1 - --- 2023-02-24 Weiwei Li New
[6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties support subsets of Float-Point in Integer Registers extensions - - 1 - --- 2021-12-24 Weiwei Li New
[6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check Improve the U/S/H extension related check - - 1 - --- 2022-07-10 Weiwei Li New
[6/7] disas/riscv.c: Fix lines with over 80 characters Add support for extension specific disas - - 1 - --- 2023-05-19 Weiwei Li New
[6/7] target/riscv: Enable PC-relative translation target/riscv: Add support for PC-relative translation - - - - --- 2023-04-09 Weiwei Li New
[6/8] target/riscv: Fix format for indentation target/riscv: Simplification for RVH related check and code style fix - - - - --- 2023-03-24 Weiwei Li New
[7/7] disas/riscv.c: Remove redundant parentheses Add support for extension specific disas - - 1 - --- 2023-05-19 Weiwei Li New
[7/7] target/riscv: Remove pc_succ_insn from DisasContext target/riscv: Add support for PC-relative translation - - - - --- 2023-04-09 Weiwei Li New
[7/8] target/riscv: Fix format for comments target/riscv: Simplification for RVH related check and code style fix 1 - - - --- 2023-03-24 Weiwei Li New
[8/8] target/riscv: Fix lines with over 80 characters target/riscv: Simplification for RVH related check and code style fix - - - - --- 2023-03-24 Weiwei Li New
[RESEND,v5,1/6] target/riscv: Fix pointer mask transformation for vector address target/riscv: Fix pointer mask related support - - 2 - --- 2023-04-01 Weiwei Li New
[RESEND,v5,2/6] target/riscv: Update cur_pmmask/base when xl changes target/riscv: Fix pointer mask related support - - 1 - --- 2023-04-01 Weiwei Li New
[RESEND,v5,3/6] target/riscv: Fix target address to update badaddr target/riscv: Fix pointer mask related support - - 1 - --- 2023-04-01 Weiwei Li New
[RESEND,v5,4/6] target/riscv: Add support for PC-relative translation target/riscv: Fix pointer mask related support - - 1 - --- 2023-04-01 Weiwei Li New
[RESEND,v5,5/6] target/riscv: Enable PC-relative translation in system mode target/riscv: Fix pointer mask related support - - 2 - --- 2023-04-01 Weiwei Li New
[RESEND,v5,6/6] target/riscv: Add pointer mask support for instruction fetch target/riscv: Fix pointer mask related support - - 1 - --- 2023-04-01 Weiwei Li New
[RESEND] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 [RESEND] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 1 - - - --- 2022-03-30 Weiwei Li New
[RFC,1/3] target/riscv: add support for svnapot extension support subsets of virtual memory extension - - - - --- 2021-11-28 Weiwei Li New
[RFC,1/5] target/riscv: Add properties for BF16 extensions target/riscv: Add support for BF16 extensions - - 1 - --- 2023-04-12 Weiwei Li New
[RFC,1/6] target/riscv: rvk: add flag support for Zbk[bcx] support subsets of scalar crypto extension - - - - --- 2021-11-02 Weiwei Li New
[RFC,1/8] target/riscv: add cfg properties for Zc* extension support subsets of code size reduction extension - - 1 - --- 2022-09-30 Weiwei Li New
[RFC,2/3] target/riscv: add support for svinval extension support subsets of virtual memory extension - - - - --- 2021-11-28 Weiwei Li New
[RFC,2/5] target/riscv: Add support for Zfbfmin extension target/riscv: Add support for BF16 extensions - - 1 - --- 2023-04-12 Weiwei Li New
[RFC,2/6] target/riscv: rvk: add implementation of instructions for Zbk* - reuse partial instructio… support subsets of scalar crypto extension - - - - --- 2021-11-02 Weiwei Li New
[RFC,2/8] target/riscv: add support for Zca, Zcf and Zcd extension support subsets of code size reduction extension - - - - --- 2022-09-30 Weiwei Li New
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