| Message ID | 20230214083833.44205-12-liweiwei@iscas.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Some updates to float point related extensions | expand |
On 2/14/23 05:38, Weiwei Li wrote: > Zvfh supports vector float point instuctions with SEW = 16 s/instuctions/instructions > and supports conversions between 8-bit integers adn binary16 values s/adn/and > > Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/insn_trans/trans_rvv.c.inc | 31 +++++++++++++++++++++++-- > 1 file changed, 29 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 9053759546..9b2c5c9ac0 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -40,6 +40,7 @@ static bool require_rvf(DisasContext *s) > > switch (s->sew) { > case MO_16: > + return s->cfg_ptr->ext_zvfh; > case MO_32: > return s->cfg_ptr->ext_zve32f; > case MO_64: > @@ -57,6 +58,25 @@ static bool require_scale_rvf(DisasContext *s) > > switch (s->sew) { > case MO_8: > + return s->cfg_ptr->ext_zvfh; > + case MO_16: > + return s->cfg_ptr->ext_zve32f; > + case MO_32: > + return s->cfg_ptr->ext_zve64d; > + default: > + return false; > + } > +} > + > +static bool require_scale_rvfmin(DisasContext *s) > +{ > + if (s->mstatus_fs == 0) { > + return false; > + } > + > + switch (s->sew) { > + case MO_8: > + return s->cfg_ptr->ext_zvfhmin; > case MO_16: > return s->cfg_ptr->ext_zve32f; > case MO_32: > @@ -2798,7 +2818,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a) > static bool opffv_widen_check(DisasContext *s, arg_rmr *a) > { > return opfv_widen_check(s, a) && > - require_scale_rvf(s) && > + require_scale_rvfmin(s) && > (s->sew != MO_8); > } > > @@ -2909,6 +2929,13 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) > } > > static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) > +{ > + return opfv_narrow_check(s, a) && > + require_scale_rvfmin(s) && > + (s->sew != MO_8); > +} > + > +static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) > { > return opfv_narrow_check(s, a) && > require_scale_rvf(s) && > @@ -2952,7 +2979,7 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w, > GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w, > RISCV_FRM_DYN) > /* Reuse the helper function from vfncvt.f.f.w */ > -GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w, > +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w, > RISCV_FRM_ROD) > > static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 9053759546..9b2c5c9ac0 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -40,6 +40,7 @@ static bool require_rvf(DisasContext *s) switch (s->sew) { case MO_16: + return s->cfg_ptr->ext_zvfh; case MO_32: return s->cfg_ptr->ext_zve32f; case MO_64: @@ -57,6 +58,25 @@ static bool require_scale_rvf(DisasContext *s) switch (s->sew) { case MO_8: + return s->cfg_ptr->ext_zvfh; + case MO_16: + return s->cfg_ptr->ext_zve32f; + case MO_32: + return s->cfg_ptr->ext_zve64d; + default: + return false; + } +} + +static bool require_scale_rvfmin(DisasContext *s) +{ + if (s->mstatus_fs == 0) { + return false; + } + + switch (s->sew) { + case MO_8: + return s->cfg_ptr->ext_zvfhmin; case MO_16: return s->cfg_ptr->ext_zve32f; case MO_32: @@ -2798,7 +2818,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a) static bool opffv_widen_check(DisasContext *s, arg_rmr *a) { return opfv_widen_check(s, a) && - require_scale_rvf(s) && + require_scale_rvfmin(s) && (s->sew != MO_8); } @@ -2909,6 +2929,13 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) } static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return opfv_narrow_check(s, a) && + require_scale_rvfmin(s) && + (s->sew != MO_8); +} + +static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && require_scale_rvf(s) && @@ -2952,7 +2979,7 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w, GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w, RISCV_FRM_DYN) /* Reuse the helper function from vfncvt.f.f.w */ -GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w, +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w, RISCV_FRM_ROD) static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)