| Message ID | 20230214083833.44205-4-liweiwei@iscas.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Some updates to float point related extensions | expand |
On 2/14/23 05:38, Weiwei Li wrote: > We needn't check Zfh and Zhinx in these instructions Nit: missing period in the end. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/insn_trans/trans_rvzfh.c.inc | 25 +++++++++++------------ > 1 file changed, 12 insertions(+), 13 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc > index 2ad5716312..85fc1aa822 100644 > --- a/target/riscv/insn_trans/trans_rvzfh.c.inc > +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc > @@ -28,15 +28,14 @@ > } \ > } while (0) > > -#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ > - if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ > +#define REQUIRE_ZFHMIN(ctx) do { \ > + if (!ctx->cfg_ptr->ext_zfhmin) { \ > return false; \ > } \ > } while (0) > > -#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \ > - if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin || \ > - ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \ > +#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do { \ > + if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \ > return false; \ > } \ > } while (0) > @@ -47,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) > TCGv t0; > > REQUIRE_FPU; > - REQUIRE_ZFH_OR_ZFHMIN(ctx); > + REQUIRE_ZFHMIN(ctx); > > decode_save_opc(ctx); > t0 = get_gpr(ctx, a->rs1, EXT_NONE); > @@ -70,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) > TCGv t0; > > REQUIRE_FPU; > - REQUIRE_ZFH_OR_ZFHMIN(ctx); > + REQUIRE_ZFHMIN(ctx); > > decode_save_opc(ctx); > t0 = get_gpr(ctx, a->rs1, EXT_NONE); > @@ -401,7 +400,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a) > static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) > { > REQUIRE_FPU; > - REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); > + REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); > > TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > @@ -418,7 +417,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) > static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) > { > REQUIRE_FPU; > - REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); > + REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); > REQUIRE_ZDINX_OR_D(ctx); > > TCGv_i64 dest = dest_fpr(ctx, a->rd); > @@ -436,7 +435,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) > static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) > { > REQUIRE_FPU; > - REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); > + REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); > > TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > @@ -452,7 +451,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) > static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a) > { > REQUIRE_FPU; > - REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); > + REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); > REQUIRE_ZDINX_OR_D(ctx); > > TCGv_i64 dest = dest_fpr(ctx, a->rd); > @@ -585,7 +584,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a) > static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) > { > REQUIRE_FPU; > - REQUIRE_ZFH_OR_ZFHMIN(ctx); > + REQUIRE_ZFHMIN(ctx); > > TCGv dest = dest_gpr(ctx, a->rd); > > @@ -605,7 +604,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) > static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a) > { > REQUIRE_FPU; > - REQUIRE_ZFH_OR_ZFHMIN(ctx); > + REQUIRE_ZFHMIN(ctx); > > TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO); >
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 2ad5716312..85fc1aa822 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -28,15 +28,14 @@ } \ } while (0) -#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ - if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ +#define REQUIRE_ZFHMIN(ctx) do { \ + if (!ctx->cfg_ptr->ext_zfhmin) { \ return false; \ } \ } while (0) -#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \ - if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin || \ - ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \ +#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do { \ + if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \ return false; \ } \ } while (0) @@ -47,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) TCGv t0; REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN(ctx); + REQUIRE_ZFHMIN(ctx); decode_save_opc(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); @@ -70,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) TCGv t0; REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN(ctx); + REQUIRE_ZFHMIN(ctx); decode_save_opc(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); @@ -401,7 +400,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a) static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); + REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); TCGv_i64 dest = dest_fpr(ctx, a->rd); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); @@ -418,7 +417,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); + REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); REQUIRE_ZDINX_OR_D(ctx); TCGv_i64 dest = dest_fpr(ctx, a->rd); @@ -436,7 +435,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); + REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); TCGv_i64 dest = dest_fpr(ctx, a->rd); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); @@ -452,7 +451,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); + REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); REQUIRE_ZDINX_OR_D(ctx); TCGv_i64 dest = dest_fpr(ctx, a->rd); @@ -585,7 +584,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a) static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN(ctx); + REQUIRE_ZFHMIN(ctx); TCGv dest = dest_gpr(ctx, a->rd); @@ -605,7 +604,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN(ctx); + REQUIRE_ZFHMIN(ctx); TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);