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[08/14] target/riscv: Simplify check for Zve32f and Zve64f

Message ID 20230214083833.44205-9-liweiwei@iscas.ac.cn
State New
Headers show
Series target/riscv: Some updates to float point related extensions | expand

Commit Message

Weiwei Li Feb. 14, 2023, 8:38 a.m. UTC 
Zve64f depends on Zve32f, so we can only check Zve32f
in these cases

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

Comments

Daniel Henrique Barboza Feb. 14, 2023, 1:25 p.m. UTC | #1 
On 2/14/23 05:38, Weiwei Li wrote:
> Zve64f depends on Zve32f, so we can only check Zve32f
> in these cases
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 8 ++------
>   1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index bbb5c3a7b5..6f7ecf1a68 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -173,9 +173,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
>   {
>       TCGv s1, dst;
>   
> -    if (!require_rvv(s) ||
> -        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
> -          s->cfg_ptr->ext_zve64f)) {
> +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
>           return false;
>       }
>   
> @@ -210,9 +208,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
>   {
>       TCGv dst;
>   
> -    if (!require_rvv(s) ||
> -        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
> -          s->cfg_ptr->ext_zve64f)) {
> +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
>           return false;
>       }
>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index bbb5c3a7b5..6f7ecf1a68 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -173,9 +173,7 @@  static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) ||
-        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
-          s->cfg_ptr->ext_zve64f)) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
         return false;
     }
 
@@ -210,9 +208,7 @@  static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) ||
-        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
-          s->cfg_ptr->ext_zve64f)) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
         return false;
     }