Message ID | 20230324123809.107714-3-liweiwei@iscas.ac.cn |
---|---|
State | New |
Headers | show |
Series | target/riscv: Simplification for RVH related check and code style fix | expand |
On 3/24/23 05:38, Weiwei Li wrote: > Check on riscv_cpu_virt_enabled contains the check on RVH. > > Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn> > --- > target/riscv/op_helper.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 84ee018f7d..1eecae9547 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -278,8 +278,7 @@ target_ulong helper_sret(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } - if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_VTSR)) { + if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTSR)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); }