| Message ID | 20230214083833.44205-5-liweiwei@iscas.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Some updates to float point related extensions | expand |
On 2/14/23 05:38, Weiwei Li wrote: > Add properties for Zve64d,Zvfh,Zvfhmin extension "for Zve64d,Zvfh,Zvfhmin extensions." > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 7128438d8e..54c6875617 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -462,7 +462,10 @@ struct RISCVCPUConfig { > bool ext_zhinxmin; > bool ext_zve32f; > bool ext_zve64f; > + bool ext_zve64d; > bool ext_zmmul; > + bool ext_zvfh; > + bool ext_zvfhmin; > bool ext_smaia; > bool ext_ssaia; > bool ext_sscofpmf;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7128438d8e..54c6875617 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -462,7 +462,10 @@ struct RISCVCPUConfig { bool ext_zhinxmin; bool ext_zve32f; bool ext_zve64f; + bool ext_zve64d; bool ext_zmmul; + bool ext_zvfh; + bool ext_zvfhmin; bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf;