diff mbox series

[U-Boot,37/40] x86: Update device tree for TPL

Message ID 20190130035935.235565-38-sjg@chromium.org
State Superseded
Delegated to: Bin Meng
Headers show
Series x86: Add support for booting from TPL | expand

Commit Message

Simon Glass Jan. 30, 2019, 3:59 a.m. UTC
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/dts/u-boot.dtsi | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

Comments

Bin Meng Feb. 22, 2019, 7:20 a.m. UTC | #1
Hi Simon,

On Wed, Jan 30, 2019 at 12:01 PM Simon Glass <sjg@chromium.org> wrote:
>
> Add TPL binaries to the device x86 binman desciption. When enabled, TPL
> will start first, doing the 16-bit init, then jump to SPL and finally
> U-Boot proper.

I am confused by "TPL will start first". My understanding is that
"SPL" starts before "TPL".

>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/dts/u-boot.dtsi | 26 ++++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
>

Regards,
Bin
Simon Glass April 3, 2019, 2:23 a.m. UTC | #2
Hi Bin,

On Fri, 22 Feb 2019 at 00:20, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Wed, Jan 30, 2019 at 12:01 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > Add TPL binaries to the device x86 binman desciption. When enabled, TPL
> > will start first, doing the 16-bit init, then jump to SPL and finally
> > U-Boot proper.
>
> I am confused by "TPL will start first". My understanding is that
> "SPL" starts before "TPL".

No, it is TPL -> SPL - > U-Boot.

Regards,
Simon
diff mbox series

Patch

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1050236330..70e9c8f7ac 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -22,7 +22,21 @@ 
 			filename = CONFIG_INTEL_ME_FILE;
 		};
 #endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+		u-boot-spl {
+			offset = <CONFIG_SPL_TEXT_BASE>;
+		};
+		u-boot-spl-dtb {
+		};
+		u-boot-tpl-with-ucode-ptr {
+			offset = <CONFIG_TPL_TEXT_BASE>;
+		};
+		u-boot-tpl-dtb {
+		};
+		u-boot {
+			offset = <CONFIG_SYS_TEXT_BASE>;
+		};
+#elif defined(CONFIG_SPL)
 		u-boot-spl-with-ucode-ptr {
 			offset = <CONFIG_SPL_TEXT_BASE>;
 		};
@@ -31,7 +45,11 @@ 
 			type = "u-boot-dtb-with-ucode";
 		};
 		u-boot {
+#if CONFIG_SYS_TEXT_BASE == 0x1110000
 			offset = <0xfff00000>;
+#else
+			offset = <CONFIG_SYS_TEXT_BASE>;
+#endif
 		};
 #else
 		u-boot-with-ucode-ptr {
@@ -77,7 +95,11 @@ 
 			offset = <CONFIG_X86_REFCODE_ADDR>;
 		};
 #endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+		x86-start16-tpl {
+			offset = <CONFIG_SYS_X86_START16>;
+		};
+#elif defined(CONFIG_SPL)
 		x86-start16-spl {
 			offset = <CONFIG_SYS_X86_START16>;
 		};