diff mbox series

[U-Boot,16/40] x86: broadwell: Improve SDRAM debugging output

Message ID 20190130035935.235565-17-sjg@chromium.org
State Superseded
Delegated to: Bin Meng
Headers show
Series x86: Add support for booting from TPL | expand

Commit Message

Simon Glass Jan. 30, 2019, 3:59 a.m. UTC 
Add debugging during SDRAM init so that problems are easier to
diagnose.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/broadwell/sdram.c | 32 ++++++++++++++++++++------------
 1 file changed, 20 insertions(+), 12 deletions(-)

Comments

Bin Meng Feb. 22, 2019, 7:19 a.m. UTC | #1 
On Wed, Jan 30, 2019 at 12:00 PM Simon Glass <sjg@chromium.org> wrote:
>
> Add debugging during SDRAM init so that problems are easier to
> diagnose.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/broadwell/sdram.c | 32 ++++++++++++++++++++------------
>  1 file changed, 20 insertions(+), 12 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 03a35bcf73..1b9f9840c6 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -204,16 +204,18 @@  int dram_init(void)
 
 	/* Print ME state before MRC */
 	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
-	if (ret)
+	if (ret) {
+		debug("Cannot get ME (err=%d)\n", ret);
 		return ret;
+	}
 	intel_me_status(me_dev);
 
 	/* Save ME HSIO version */
-	ret = uclass_first_device(UCLASS_PCH, &pch_dev);
-	if (ret)
+	ret = uclass_first_device_err(UCLASS_PCH, &pch_dev);
+	if (ret) {
+		debug("Cannot get PCH (err=%d)\n", ret);
 		return ret;
-	if (!pch_dev)
-		return -ENODEV;
+	}
 	power_state_get(pch_dev, &ps);
 
 	intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
@@ -221,15 +223,17 @@  int dram_init(void)
 	broadwell_fill_pei_data(pei_data);
 	mainboard_fill_pei_data(pei_data);
 
-	ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
-	if (ret)
+	ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
+	if (ret) {
+		debug("Cannot get Northbridge (err=%d)\n", ret);
 		return ret;
-	if (!dev)
-		return -ENODEV;
+	}
 	size = 256;
 	ret = mrc_locate_spd(dev, size, &spd_data);
-	if (ret)
+	if (ret) {
+		debug("Cannot locate SPD (err=%d)\n", ret);
 		return ret;
+	}
 	memcpy(pei_data->spd_data[0][0], spd_data, size);
 	memcpy(pei_data->spd_data[1][0], spd_data, size);
 
@@ -239,13 +243,17 @@  int dram_init(void)
 
 	debug("PEI version %#x\n", pei_data->pei_version);
 	ret = mrc_common_init(dev, pei_data, true);
-	if (ret)
+	if (ret) {
+		debug("mrc_common_init() failed(err=%d)\n", ret);
 		return ret;
+	}
 	debug("Memory init done\n");
 
 	ret = sdram_find(dev);
-	if (ret)
+	if (ret) {
+		debug("sdram_find() failed (err=%d)\n", ret);
 		return ret;
+	}
 	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
 	debug("RAM size %llx\n", (unsigned long long)gd->ram_size);