Show patches with: none      |   179582 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[U-Boot,1/4] x86: Make sure i8254 is setup correctly before generating beeps [U-Boot,1/4] x86: Make sure i8254 is setup correctly before generating beeps - - 1 - --- 2019-02-26 Bin Meng bmeng Accepted
[U-Boot] Please pull u-boot-x86 [U-Boot] Please pull u-boot-x86 - - - - --- 2019-02-20 Bin Meng trini Accepted
[U-Boot] Please pull u-boot-x86 [U-Boot] Please pull u-boot-x86 - - - - --- 2019-02-12 Bin Meng trini Accepted
[U-Boot,3/3] x86: Use the existing GDT in the ROM for 64-bit U-Boot proper [U-Boot,1/3] x86: Change 4-level page table base address to low memory - - 1 - --- 2019-01-31 Bin Meng bmeng Accepted
[U-Boot,2/3] x86: Don't copy the cpu_call64() function to a hardcoded address [U-Boot,1/3] x86: Change 4-level page table base address to low memory - - 1 - --- 2019-01-31 Bin Meng bmeng Accepted
[U-Boot,1/3] x86: Change 4-level page table base address to low memory [U-Boot,1/3] x86: Change 4-level page table base address to low memory - - 1 1 --- 2019-01-31 Bin Meng bmeng Accepted
[U-Boot] Please pull u-boot-x86 [U-Boot] Please pull u-boot-x86 - - - - --- 2018-12-31 Bin Meng trini Accepted
[U-Boot,4/4] fs: cbfs: Add missing standard CBFS component types [U-Boot,1/4] fs: cbfs: remove wrong header validation - - 1 - --- 2018-12-22 Bin Meng bmeng Accepted
[U-Boot,3/4] fs: cbfs: Make all CBFS_TYPE_xxx macros consistent [U-Boot,1/4] fs: cbfs: remove wrong header validation - - 1 - --- 2018-12-22 Bin Meng bmeng Accepted
[U-Boot,2/4] fs: cbfs: Fix out of bound access during CBFS walking through [U-Boot,1/4] fs: cbfs: remove wrong header validation - - 1 - --- 2018-12-22 Bin Meng bmeng Accepted
[U-Boot,1/4] fs: cbfs: remove wrong header validation [U-Boot,1/4] fs: cbfs: remove wrong header validation - - 1 - --- 2018-12-22 Bin Meng bmeng Accepted
[U-Boot,3/3] riscv: bootm: Support booting VxWorks [U-Boot,1/3] bootm: vxworks: Make do_bootvx_fdt() static - - - - --- 2018-12-21 Bin Meng trini Accepted
[U-Boot,2/3] bootm: vxworks: Make do_bootm_vxworks() non-static [U-Boot,1/3] bootm: vxworks: Make do_bootvx_fdt() static - - - - --- 2018-12-21 Bin Meng trini Accepted
[U-Boot,1/3] bootm: vxworks: Make do_bootvx_fdt() static [U-Boot,1/3] bootm: vxworks: Make do_bootvx_fdt() static - - - - --- 2018-12-21 Bin Meng trini Accepted
[U-Boot] riscv: bootm: Support booting VxWorks [U-Boot] riscv: bootm: Support booting VxWorks - - - - --- 2018-12-21 Bin Meng Superseded
[U-Boot,v5,25/25] riscv: Remove ae350.dts riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,24/25] riscv: bootm: Change to use boot_hart from global data riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,23/25] riscv: Save boot hart id to the global data riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,22/25] riscv: Adjust the _exit_trap() position to come before handle_trap() riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,21/25] riscv: Return to previous privilege level after trap handling riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,20/25] riscv: Fix context restore before returning from trap handler riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,19/25] riscv: Move trap handler codes to mtrap.S riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,18/25] riscv: Do some basic architecture level cpu initialization riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,17/25] riscv: Add indirect stringification to csr_xxx ops riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,16/25] riscv: Update supports_extension() to use desc from cpu driver riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,15/25] riscv: Add exception codes for xcause register riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,14/25] riscv: Add CSR numbers riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,13/25] riscv: Remove non-DM version of print_cpuinfo() riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,12/25] riscv: Probe cpus during boot riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,11/25] riscv: Enlarge the default SYS_MALLOC_F_LEN riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,10/25] riscv: qemu: Add platform-specific Kconfig options riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,09/25] riscv: Implement riscv_get_time() API using rdtime instruction riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,08/25] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,07/25] riscv: Introduce a Kconfig option for machine mode riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,06/25] riscv: ax25: Hide the ax25-specific Kconfig option riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,05/25] timer: Add generic driver for RISC-V privileged architecture defined timer riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,04/25] cpu: Add a RISC-V CPU driver riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,03/25] riscv: qemu: Create a simple-bus driver for the soc node riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,02/25] dm: cpu: Add timebase frequency to the platdata riscv: Adding RISC-V CPU and timer driver - - 3 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v5,01/25] riscv: add Kconfig entries for the code model riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Accepted
[U-Boot,v4,25/25] riscv: Remove ae350.dts riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,24/25] riscv: bootm: Change to use boot_hart from global data riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,23/25] riscv: Save boot hart id to the global data riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,22/25] riscv: Adjust the _exit_trap() position to come before handle_trap() riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,21/25] riscv: Return to previous privilege level after trap handling riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,20/25] riscv: Fix context restore before returning from trap handler riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,19/25] riscv: Move trap handler codes to mtrap.S riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,18/25] riscv: Do some basic architecture level cpu initialization riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,17/25] riscv: Add indirect stringification to csr_xxx ops riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,16/25] riscv: Update supports_extension() to use desc from cpu driver riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,15/25] riscv: Add exception codes for xcause register riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,14/25] riscv: Add CSR numbers riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,13/25] riscv: Remove non-DM version of print_cpuinfo() riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,12/25] riscv: Probe cpus during boot riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,11/25] riscv: Enlarge the default SYS_MALLOC_F_LEN riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,10/25] riscv: qemu: Add platform-specific Kconfig options riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,09/25] riscv: Implement riscv_get_time() API using rdtime instruction riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,08/25] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,07/25] riscv: Introduce a Kconfig option for machine mode riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,06/25] riscv: ax25: Hide the ax25-specific Kconfig option riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,05/25] timer: Add generic driver for RISC-V privileged architecture defined timer riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,04/25] cpu: Add a RISC-V CPU driver riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,03/25] riscv: qemu: Create a simple-bus driver for the soc node riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,02/25] dm: cpu: Add timebase frequency to the platdata riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v4,01/25] riscv: add Kconfig entries for the code model riscv: Adding RISC-V CPU and timer driver - - - - --- 2018-12-12 Bin Meng Andes Superseded
[U-Boot,v3,25/25] riscv: Remove ae350.dts riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,24/25] riscv: bootm: Change to use boot_hart from global data riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,23/25] riscv: Save boot hart id to the global data riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,22/25] riscv: Adjust the _exit_trap() position to come before handle_trap() riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,21/25] riscv: Return to previous privilege level after trap handling riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,20/25] riscv: Fix context restore before returning from trap handler riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,19/25] riscv: Move trap handler codes to mtrap.S riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,18/25] riscv: Do some basic architecture level cpu initialization riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,17/25] riscv: Add indirect stringification to csr_xxx ops riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,16/25] riscv: Update supports_extension() to use desc from cpu driver riscv: Adding RISC-V CPU and timer driver - - - - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,15/25] riscv: Add exception codes for xcause register riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,14/25] riscv: Add CSR numbers riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,13/25] riscv: Remove non-DM version of print_cpuinfo() riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,12/25] riscv: Probe cpus during boot riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,11/25] riscv: Enlarge the default SYS_MALLOC_F_LEN riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,10/25] riscv: qemu: Add platform-specific Kconfig options riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,09/25] riscv: Implement riscv_get_time() API using rdtime instruction riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,08/25] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,07/25] riscv: Introduce a Kconfig option for machine mode riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,06/25] riscv: ax25: Hide the ax25-specific Kconfig option riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,05/25] timer: Add generic driver for RISC-V privileged architecture defined timer riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,04/25] cpu: Add a RISC-V CPU driver riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,03/25] riscv: qemu: Create a simple-bus driver for the soc node riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,02/25] dm: cpu: Add timebase frequency to the platdata riscv: Adding RISC-V CPU and timer driver - - 2 - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot,v3,01/25] riscv: add Kconfig entries for the code model riscv: Adding RISC-V CPU and timer driver - - - - --- 2018-12-11 Bin Meng Andes Superseded
[U-Boot] Please pull u-boot-x86 [U-Boot] Please pull u-boot-x86 - - - - --- 2018-12-10 Bin Meng trini Accepted
[U-Boot,v2,20/20] riscv: Adjust the _exit_trap() position to come before handle_trap() riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-07 Bin Meng Andes Superseded
[U-Boot,v2,19/20] riscv: Return to previous privilege level after trap handling riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-07 Bin Meng Andes Superseded
[U-Boot,v2,18/20] riscv: Fix context restore before returning from trap handler riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-07 Bin Meng Andes Superseded
[U-Boot,v2,17/20] riscv: Move trap handler codes to mtrap.S riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-07 Bin Meng Andes Superseded
[U-Boot,v2,16/20] riscv: Do some basic architecture level cpu initialization riscv: Adding RISC-V CPU and timer driver - - - - --- 2018-12-07 Bin Meng Andes Superseded
[U-Boot,v2,15/20] riscv: Add indirect stringification to csr_xxx ops riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-07 Bin Meng Andes Superseded
[U-Boot,v2,14/20] riscv: Add exception codes for xcause register riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-07 Bin Meng Andes Superseded
[U-Boot,v2,13/20] riscv: Add CSR numbers riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-07 Bin Meng Andes Superseded
[U-Boot,v2,12/20] riscv: Probe cpus during boot riscv: Adding RISC-V CPU and timer driver - - 1 - --- 2018-12-07 Bin Meng Andes Superseded
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