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[U-Boot,v5,18/25] riscv: Do some basic architecture level cpu initialization

Message ID 1544623967-30010-19-git-send-email-bmeng.cn@gmail.com
State Accepted
Delegated to: Andes
Headers show
Series riscv: Adding RISC-V CPU and timer driver | expand

Commit Message

Bin Meng Dec. 12, 2018, 2:12 p.m. UTC 
In arch_cpu_init_dm() do some basic architecture level cpu
initialization, like FPU enable, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>

---

Changes in v5: None
Changes in v4: None
Changes in v3:
- only initialize mcounteren CSR for S-mode
- only touch satp in M-mode U-Boot
- move the implementation to arch_cpu_init_dm()

Changes in v2:
- use csr_set() to set MSTATUS_FS
- only enabling the cycle, time, and instret counters
- change to use satp

 arch/riscv/cpu/cpu.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index fc7c9b3..e662140 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -8,6 +8,7 @@ 
 #include <dm.h>
 #include <log.h>
 #include <asm/csr.h>
+#include <asm/encoding.h>
 #include <dm/uclass-internal.h>
 
 /*
@@ -61,7 +62,31 @@  static int riscv_cpu_probe(void)
 
 int arch_cpu_init_dm(void)
 {
-	return riscv_cpu_probe();
+	int ret;
+
+	ret = riscv_cpu_probe();
+	if (ret)
+		return ret;
+
+	/* Enable FPU */
+	if (supports_extension('d') || supports_extension('f')) {
+		csr_set(MODE_PREFIX(status), MSTATUS_FS);
+		csr_write(fcsr, 0);
+	}
+
+	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
+		/*
+		 * Enable perf counters for cycle, time,
+		 * and instret counters only
+		 */
+		csr_write(mcounteren, GENMASK(2, 0));
+
+		/* Disable paging */
+		if (supports_extension('s'))
+			csr_write(satp, 0);
+	}
+
+	return 0;
 }
 
 int arch_early_init_r(void)