diff mbox series

[v3,14/40] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)

Message ID 1532004912-13899-15-git-send-email-stefan.markovic@rt-rk.com
State New
Headers show
Series Add nanoMIPS support to QEMU | expand

Commit Message

Stefan Markovic July 19, 2018, 12:54 p.m. UTC 
From: Yongbok Kim <yongbok.kim@mips.com>

Add emulation of misc nanoMIPS instructions situated in pool32axf.

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

Comments

Richard Henderson July 19, 2018, 7:13 p.m. UTC | #1 
On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> +static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
> +{
> +    int rt = (ctx->opcode >> 21) & 0x1f;
> +    int rs = (ctx->opcode >> 16) & 0x1f;
> +
> +    switch ((ctx->opcode >> 6) & 0x07) {

extract32.

>          case NM_POOL32A7:
> +        {
> +            switch ((ctx->opcode >> 3) & 0x07) {
> +            case NM_POOL32AXF:
> +                gen_pool32axf_nanomips_insn(env, ctx);
> +                break;
> +            }
> +        }

Bad indentation of a block that need not exist anyway.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
Aleksandar Markovic July 20, 2018, 4:15 p.m. UTC | #2 
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Thursday, July 19, 2018 9:13 PM
>
> >          case NM_POOL32A7:
> > +        {
> > +            switch ((ctx->opcode >> 3) & 0x07) {
> > +            case NM_POOL32AXF:
> > +                gen_pool32axf_nanomips_insn(env, ctx);
> > +                break;
> > +            }
> > +        }
>
> Bad indentation of a block that need not exist anyway.
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Outer braces are unnecessary. The switch is missing the default case. This switch statement is amended in one of subsequent patches, and at the end it contains four cases, but no default case. The missing default should be fixed in this patch.
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 81c2950..af7825a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16768,6 +16768,93 @@  static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
     }
 }
 
+static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
+{
+    int rt = (ctx->opcode >> 21) & 0x1f;
+    int rs = (ctx->opcode >> 16) & 0x1f;
+
+    switch ((ctx->opcode >> 6) & 0x07) {
+    case NM_POOL32AXF_4:
+    case NM_POOL32AXF_5:
+        switch ((ctx->opcode >> 9) & 0x7f) {
+        case NM_CLO:
+            gen_cl(ctx, OPC_CLO, rt, rs);
+            break;
+        case NM_CLZ:
+            gen_cl(ctx, OPC_CLZ, rt, rs);
+            break;
+#ifndef CONFIG_USER_ONLY
+        case NM_TLBP:
+            gen_cp0(env, ctx, OPC_TLBP, 0, 0);
+            break;
+        case NM_TLBR:
+            gen_cp0(env, ctx, OPC_TLBR, 0, 0);
+            break;
+        case NM_TLBWI:
+            gen_cp0(env, ctx, OPC_TLBWI, 0, 0);
+            break;
+        case NM_TLBWR:
+            gen_cp0(env, ctx, OPC_TLBWR, 0, 0);
+            break;
+        case NM_TLBINV:
+            gen_cp0(env, ctx, OPC_TLBINV, 0, 0);
+            break;
+        case NM_TLBINVF:
+            gen_cp0(env, ctx, OPC_TLBINVF, 0, 0);
+            break;
+        case NM_DI:
+            check_cp0_enabled(ctx);
+            {
+                TCGv t0 = tcg_temp_new();
+
+                save_cpu_state(ctx, 1);
+                gen_helper_di(t0, cpu_env);
+                gen_store_gpr(t0, rt);
+            /* Stop translation as we may have switched the execution mode */
+                ctx->base.is_jmp = DISAS_STOP;
+                tcg_temp_free(t0);
+            }
+            break;
+        case NM_EI:
+            check_cp0_enabled(ctx);
+            {
+                TCGv t0 = tcg_temp_new();
+
+                save_cpu_state(ctx, 1);
+                gen_helper_ei(t0, cpu_env);
+                gen_store_gpr(t0, rt);
+            /* Stop translation as we may have switched the execution mode */
+                ctx->base.is_jmp = DISAS_STOP;
+                tcg_temp_free(t0);
+            }
+            break;
+        case NM_RDPGPR:
+            gen_load_srsgpr(rs, rt);
+            break;
+        case NM_WRPGPR:
+            gen_store_srsgpr(rs, rt);
+            break;
+        case NM_WAIT:
+            gen_cp0(env, ctx, OPC_WAIT, 0, 0);
+            break;
+        case NM_DERET:
+            gen_cp0(env, ctx, OPC_DERET, 0, 0);
+            break;
+        case NM_ERETX:
+            gen_cp0(env, ctx, OPC_ERET, 0, 0);
+            break;
+#endif
+        default:
+            generate_exception_end(ctx, EXCP_RI);
+            break;
+        }
+        break;
+    default:
+        generate_exception_end(ctx, EXCP_RI);
+        break;
+    }
+}
+
 static void gen_pool32f_nanomips_insn(DisasContext *ctx)
 {
     int rt, rs, rd;
@@ -17137,6 +17224,13 @@  static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_pool32a0_nanomips_insn(ctx);
             break;
         case NM_POOL32A7:
+        {
+            switch ((ctx->opcode >> 3) & 0x07) {
+            case NM_POOL32AXF:
+                gen_pool32axf_nanomips_insn(env, ctx);
+                break;
+            }
+        }
             break;
         default:
             generate_exception_end(ctx, EXCP_RI);